dff.v

来自「(2,1,9)卷积编解码器」· Verilog 代码 · 共 17 行

module pDFF(DATA,QOUT,CLOCK,RESET);


parameter WIDTH = 1; 

input [WIDTH-1:0] DATA;
input CLOCK, RESET;

output [WIDTH-1:0] QOUT;

reg [WIDTH-1:0] QOUT;

   always @(posedge CLOCK or negedge RESET)
      if (~RESET) QOUT <= 0; //active low reset
         else QOUT <= DATA;

endmodule