pctest.v

关于verilog的各个基本模块的源代码

module pctest;

wire [4:0]pcout;
reg [4:0]pcin;
reg writepc,clk,rst;

pc pct(pcout,pcin,writepc,clk,rst);

always #50 clk=~clk;

initial
	begin
		clk=0;
		rst=0;
     pcin=5'b00101;
#50  writepc=1;
     rst=0;
#50  writepc=0;
     rst=1;
#200 $stop;
end

endmodule