mux41_32test.v

关于verilog的各个基本模块的源代码

module mux41_32test;

reg [31:0]a,b,c,d;
reg [1:0]s;
wire [31:0]e;

mux41_32 mux3(e,a,b,c,d,s);

initial
  begin
  a=32'b0010_1101_0011_0000_1101_1111_1101_0000;
  b=32'b1011_1100_0001_0010_1100_1101_1100_0010;
  c=32'b0010_1001_0111_0110_1001_1001_1111_0100;
  d=32'b0010_1000_0111_0111_1001_1000_1100_0111;
#50 s=2'd0;
#50 s=2'd1;
#50 s=2'd2;
#50 s=2'd3;
#250 $stop;
  end

endmodule