alutest.v

关于verilog的各个基本模块的源代码

module ALUtest;

reg [1:0]op;
reg [31:0]a,b;
wire [31:0]s;
wire n,v,c,z;
//op=00 AND;
//op=01 OR;
//op=10 ADD;
//op=11 SUB;
ALU A(op,a,b,s,n,v,c,z);
initial
  begin
#50 a=32'b0100_0101_0100_0000_0010_0010_0101_0001;
    b=32'b1010_0101_0010_0000_0100_0010_0011_0010;
    op=2'b00;
#50 a=32'b0100_0101_0100_0000_0010_0010_0101_0001;
    b=32'b1010_0101_0010_0000_0100_0010_0011_0010;
    op=2'b01;
#50 a=32'b0100_0101_0100_0000_0010_0010_0101_0001;
    b=32'b1010_0101_0010_0000_0100_0010_0011_0010;
    op=2'b10;
#50 a=32'b0100_0101_0100_0000_0010_0010_0101_0001;
    b=32'b1010_0101_0010_0000_0100_0010_0011_0010;
    op=2'b11;
#50 a=32'b1111_1111_1111_1111_1111_1111_1111_1111;
    b=32'b1111_1111_1111_1111_1111_1111_1111_1111;
    op=2'b11;
#50 $stop;
  end
endmodule