mux21_32test.v

关于verilog的各个基本模块的源代码

module mux21_32test;

reg [31:0]a,b;
reg s;
wire [31:0]f;

mux21_32 mux1(f,a,b,s);

initial
begin
   a=32'b0000_0000_1010_0011_1101_1111_0010_1001;
   b=32'b0000_0000_1010_0011_1101_1111_1111_0000;
#50 s=0;
#50 s=1;
#150 $stop;
end

endmodule