top_test.v

关于verilog的各个基本模块的源代码

module TOP_test;

reg clk,rst,start,memwe;
reg [31:0] memin;
reg [4:0] memaddr;

wire n,v,c;
wire [31:0] dataout;

TOP u(clk,rst,start,memwe,memin,memaddr,n,v,c,dataout);

always #50 clk=~clk;

initial
  begin
     clk=1;
#20  rst=1;
     start=0;
  
#100 rst=0;
     memwe=1;
     memin=32'b001000_00000_11111_0000000000010000;
     memaddr=5'd0;
#100 memwe=1;
     memin=32'b001001_00000_11111_0000000000010001;
     memaddr=5'd1;
#100 memwe=1;
     memin=32'b001000_00001_11111_0000000000010001;
     memaddr=5'd2;
#100 memwe=1;
     memin=32'hFFFF_FFFF;
     memaddr=5'd16;
#100 
     memwe=0;
     start=1;

#100 start=0;

#400 rst=1;
     start=0;
#100 rst=0;
     memwe=1;
     memin=32'b0101_1010_1111_0010_1001_1000_0011_0000;
     memaddr=5'd30;
#100 memwe=1;
     memin=32'b0111_1000_1101_0110_1011_1011_0011_0101;
     memaddr=5'd31;
#100 memwe=1;
     memin=32'b001000_00000_11111_0000000000011110;
     memaddr=5'd1;
#100 memwe=1;
     memin=32'b001000_00001_11110_0000000000011111;
     memaddr=5'd2;
#100 memwe=1;
     memin=32'b000000_00010_00000_00000000000_00001;
     memaddr=5'd3;
#100 memwe=1;
     memin=32'b000010_00011_00000_00000000000_00001;
     memaddr=5'd4;
#100 memwe=1;
     memin=32'b000100_00100_00000_00000000000_00001;
     memaddr=5'd5;
#100 memwe=1;
     memin=32'b000110_00101_00000_00000000000_00001;
     memaddr=5'd6;
#100 memwe=0;
     start=1;
#100 start=0;
#12000 $stop;
end

endmodule