adder8b.vhd

实现了VHDL乘法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8b is port (
    cin : in std_logic;
      a : in std_logic_vector(7 downto 0);
      b : in std_logic_vector(7 downto 0);
      s : out std_logic_vector(7 downto 0);
   cout : out std_logic);
end adder8b;
architecture struc of adder8b is
component adder4b port(
     cin : in std_logic;
       a : in std_logic_vector(3 downto 0);
       b : in std_logic_vector(3 downto 0);
       s : out std_logic_vector(3 downto 0);
    cout : out std_logic);
end component;   
   signal carry_out : std_logic;
begin
   u1 : adder4b port map(cin, a(3 downto 0), b(3 downto 0), s(3 downto 0), carry_out);
   u2 : adder4b port map(carry_out, a(7 downto 4), b(7 downto 4), s(7 downto 4), cout);
end struc;