vga_controller.v

vga显示源码

//***************************************************************************
// Filename:  vga_controller.v
//
// Module for a simple vga controller. A "horizontal counter" counts pixels 
// in a line, including the sync pulse, front porch, back porch, etc. Then, 
// a "pulse generator" looks at the output of the counter and outputs a 
// pulse of a given length starting at a given count. These are used to 
// generate the sync pulse and the active video signal. Parameters for 
// the counter and pulse generators appear below.
//
// The logic for vertical is similar. The main difference is that the 
// vertical counter has a clock enable, which is used to make the vert 
// counter count lines instead of pixels. Specifically, the hsync from 
// the horizontal stage (which occurs once per line) creates a 1-cycle 
// pulse for the vert counter clock enable, and thus the vert counter 
// increments on every hsync.
//
// The default parameters are for 800x600 @ 72 Hz (assuming a 50 MHz clock). 
// For 640x480 @ 60 Hz, use the following (assuming a 25 MHz clock):
//
//   parameter N1       = 10;
//   parameter HCOUNT   = 800;
//   parameter HS_START = 8;
//   parameter HS_LEN   = 96;
//   parameter HA_START = 127;
//   parameter HA_LEN   = 640;
//
//   parameter N2 = 10;
//   parameter VCOUNT = 525;
//   parameter VS_START = 2;
//   parameter VS_LEN   = 2;
//   parameter VA_START = 24;
//   parameter VA_LEN   = 480;
//
// In general, you can play around with the start counts for the sync pulse 
// and active signal. This basically increases/decreases the front and back 
// porches, thereby moving the frame up/down or left/right on the screen.
//***************************************************************************
module vga_controller(clk, reset, hsync, vsync, red, green, blue);
  // parameters for horizontal
  parameter N1       = 11;    // number of counter bits
  parameter HCOUNT   = 1040;  // total pixel count
  parameter HS_START = 40;    // start of hsync pulse
  parameter HS_LEN   = 120;   // length of hsync pulse
  parameter HA_START = 224;   // start of active video
  parameter HA_LEN   = 800;   // length of active video

  // parameters for vertical
  parameter N2 = 10;          // number of counter bits
  parameter VCOUNT = 666;     // total line count
  parameter VS_START = 24;    // start of vsync pulse
  parameter VS_LEN   = 6;     // length of vsync pulse
  parameter VA_START = 64;    // start of active video
  parameter VA_LEN   = 600;   // length of active video

  input clk, reset;
  output hsync, vsync;
  output [1:0] red;
  output [1:0] green;
  output [1:0] blue;

  //***
  // Sync pulse stuff ...
  //***
  wire htc, vtc, vce;
  wire hactive, vactive;
  wire [N1-1:0] hcnt;
  wire [N2-1:0] vcnt;

  // horizontal
  counter_tc #(N1,HCOUNT)	     H_CNT(clk, reset, hcnt, htc);
  pulse_gen #(N1,HS_START,HS_LEN)  H_SYNC(clk, reset, hcnt, hsync);
  pulse_gen #(N1,HA_START,HA_LEN)  H_ACTIVE(clk, reset, hcnt, hactive);

  // vertical
  pulse_high_low                   V_CNT_CE(clk, reset, hsync, vce);
  counter_tc_ce #(N2,VCOUNT)	     V_CNT(clk, reset, vce, vcnt, vtc);
  pulse_gen #(N2,VS_START,VS_LEN)  V_SYNC(clk, reset, vcnt, vsync);
  pulse_gen #(N2,VA_START,VA_LEN)  V_ACTIVE(clk, reset, vcnt, vactive);

  //***
  // RGB stuff ...
  //***
  wire [1:0] R;
  wire [1:0] G;
  wire [1:0] B;

  // make rgb pattern
  assign R = hcnt[8:7] + vcnt[4:3];
  assign G = hcnt[6:5];
  assign B = hcnt[4:3];

  reg [1:0] red;
  reg [1:0] green;
  reg [1:0] blue;

  // gate rgb with active signals
  always @(posedge clk)
    begin
      red[1]   <= R[1] && hactive && vactive;  red[0]   <= R[0] && hactive && vactive;
      green[1] <= G[1] && hactive && vactive;  green[0] <= G[0] && hactive && vactive;
      blue[1]  <= B[1] && hactive && vactive;  blue[0]  <= B[0] && hactive && vactive;
    end
endmodule