vga_top.v

来自「vga显示源码」· Verilog 代码 · 共 56 行

//***************************************************************************
// Filename:  vga_top.v
//
// Top-level file for the vga controller assignment. Instantiates two 
// controllers: one for 800x600 @ 72 Hz and one for 640x480 @ 60 Hz. 
// Selection of a particular controller is made via the switch_n input, 
// which can be connected to one of the DIP switches on the XSA board 
// (for example). The clock is expected to be 50 MHz.
//***************************************************************************
module vga_top(clk, reset_n, switch_n, hsync_n, vsync_n, red, green, blue);
  input clk, reset_n, switch_n;
  output vsync_n, hsync_n;
  output [1:0] red;
  output [1:0] green;
  output [1:0] blue;

  // want active-high reset
  wire reset;
  assign reset = ~reset_n;

  //***
  // 800x600 controller ...
  //***
  wire vsync_a, hsync_a;
  wire [1:0] red_a;
  wire [1:0] green_a;
  wire [1:0] blue_a;
  vga_controller VGA_800(clk, reset, hsync_a, vsync_a, red_a, green_a, blue_a);

  // 640x480 expects 25 MHz, so divide 50 Mhz by two
  reg clk_div2;
  always @(posedge clk)
    if (reset) clk_div2 <= 0;
    else clk_div2 <= clk_div2 + 1'b01;

  //***
  // 640x480 controller ...
  //***
  wire vsync_b, hsync_b;
  wire [1:0] red_b;
  wire [1:0] green_b;
  wire [1:0] blue_b;
  // see vga_controller module for more info on the magic numbers below
  vga_controller #(10,800,8,96,127,640,  10,525,2,2,24,480) VGA_640(clk_div2, reset, hsync_b, vsync_b, red_b, green_b, blue_b);

  // use mux and switch_n to select a or b
  assign red = (~switch_n) ? red_a : red_b;
  assign green = (~switch_n) ? green_a : green_b;
  assign blue = (~switch_n) ? blue_a : blue_b;

  // sync pulses are negative
  assign hsync_n = (~switch_n) ? ~hsync_a : ~hsync_b;
  assign vsync_n = (~switch_n) ? ~vsync_a : ~vsync_b;

endmodule