pulse_high_low.v

来自「vga显示源码」· Verilog 代码 · 共 27 行

//********************************************************
// Filename:  pulse_high_low.v
//
// Outputs a 1-cycle pulse when din transitions from 
// high to low. Sync reset. Output is registered.
//********************************************************
module pulse_high_low(clk,reset,din,pulse);
  input clk, reset, din;
  output pulse;
  reg pulse;
  reg din_reg;

  // 1-cycle delay reg
  always @(posedge clk)
    if (reset) din_reg <= 0;
    else din_reg <= din;

  // check for old value high, current value low
  always @(posedge clk)
    if (reset) pulse <= 0;
    else
      begin
        if (~din && din_reg) pulse <= 1;
        else pulse <= 0;
      end
endmodule