pulse_gen.v

来自「vga显示源码」· Verilog 代码 · 共 31 行

//********************************************************
// Filename:  pulse_gen.v
//
// Parameterized pulse_gen module with sync reset. 
// The output is registered.
//
// Basically, just a comparator that outputs a one 
// when the count falls between two values and a 
// zero otherwise. START + LENGTH should fall within 
// the counter range (plus one). That is, this module 
// doesn't deal with counter rollover.
//********************************************************
module pulse_gen(clk,reset,count,pulse);
  parameter N = 8;      // number of counter bits
  parameter START = 0;  // start count
  parameter LENGTH = 1; // pulse length (number of cycles)

  input clk, reset;
  input [N-1:0] count;
  output pulse;
  reg pulse;

  always @(posedge clk)
    if (reset) pulse <= 0;
    else
      begin
        if ((count>=START)&&(count<START+LENGTH)) pulse <= 1;
        else pulse <= 0;
      end
endmodule