secondwatch.hier_info

用VERILOG实现的秒表 用VERILOG实现的秒表

|secondwatch
clkin => clkin~0.IN1
reset_n => reset.IN3
key[0] => ~NO_FANOUT~
key[1] => ~NO_FANOUT~
key[2] => ~NO_FANOUT~
key[3] => ~NO_FANOUT~
key[4] => ~NO_FANOUT~
key[5] => ~NO_FANOUT~
key[6] => ~NO_FANOUT~
key[7] => ~NO_FANOUT~
key[8] => ~NO_FANOUT~
switch[3] => ~NO_FANOUT~
switch[2] => ~NO_FANOUT~
switch[1] => ~NO_FANOUT~
switch[0] => ~NO_FANOUT~
led[7] <= <VCC>
led[6] <= <VCC>
led[5] <= <VCC>
led[4] <= <VCC>
led[3] <= <VCC>
led[2] <= <VCC>
led[1] <= <VCC>
led[0] <= <VCC>
seven[0] <= decode4_7:decode4_7_sl.seg
seven[1] <= decode4_7:decode4_7_sl.seg
seven[2] <= decode4_7:decode4_7_sl.seg
seven[3] <= decode4_7:decode4_7_sl.seg
seven[4] <= decode4_7:decode4_7_sl.seg
seven[5] <= decode4_7:decode4_7_sl.seg
seven[6] <= decode4_7:decode4_7_sl.seg
seven[7] <= decode4_7:decode4_7_sl.seg
seven_sel[3] <= sel[0].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[2] <= sel[1].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[1] <= sel[2].DB_MAX_OUTPUT_PORT_TYPE
seven_sel[0] <= sel[3].DB_MAX_OUTPUT_PORT_TYPE
mem_addr[0] <= <GND>
mem_addr[1] <= <GND>
mem_addr[2] <= <GND>
mem_addr[3] <= <GND>
mem_addr[4] <= <GND>
mem_addr[5] <= <GND>
mem_addr[6] <= <GND>
mem_addr[7] <= <GND>
mem_addr[8] <= <GND>
mem_addr[9] <= <GND>
mem_addr[10] <= <GND>
mem_addr[11] <= <GND>
mem_addr[12] <= <GND>
mem_addr[13] <= <GND>
mem_addr[14] <= <GND>
mem_addr[15] <= <GND>
mem_addr[16] <= <GND>
mem_addr[17] <= <GND>
mem_addr[18] <= <GND>
mem_addr[19] <= <GND>
mem_addr[20] <= <GND>
mem_data[0] <= mem_data~32
mem_data[1] <= mem_data~31
mem_data[2] <= mem_data~30
mem_data[3] <= mem_data~29
mem_data[4] <= mem_data~28
mem_data[5] <= mem_data~27
mem_data[6] <= mem_data~26
mem_data[7] <= mem_data~25
mem_data[8] <= mem_data~24
mem_data[9] <= mem_data~23
mem_data[10] <= mem_data~22
mem_data[11] <= mem_data~21
mem_data[12] <= mem_data~20
mem_data[13] <= mem_data~19
mem_data[14] <= mem_data~18
mem_data[15] <= mem_data~17
sram_be[0] <= <GND>
sram_be[1] <= <GND>
sram_rd <= <GND>
sram_wr <= <GND>
sram_sel <= <GND>
flash_oe <= <VCC>
flash_we <= <GND>
flash_cs <= <VCC>
lcd_data[0] <= lcd_data~15
lcd_data[1] <= lcd_data~14
lcd_data[2] <= lcd_data~13
lcd_data[3] <= lcd_data~12
lcd_data[4] <= lcd_data~11
lcd_data[5] <= lcd_data~10
lcd_data[6] <= lcd_data~9
lcd_data[7] <= lcd_data~8
lcd_cs1 <= <GND>
lcd_cs2 <= <GND>
lcd_di <= <GND>
lcd_e <= <GND>
lcd_reset <= <GND>
lcd_rw <= <GND>
ps2_clk <= <GND>
ps2_data <= <GND>
ps2_2_clk <= <GND>
ps2_2_data <= <GND>
rxd => ~NO_FANOUT~
txd <= <GND>
rxd_2 => ~NO_FANOUT~
txd_2 <= <GND>
motor_counter => ~NO_FANOUT~
motor_pwm <= <GND>
da_a0 <= <GND>
da_a1 <= <GND>
da_data[0] <= <GND>
da_data[1] <= <GND>
da_data[2] <= <GND>
da_data[3] <= <GND>
da_data[4] <= <GND>
da_data[5] <= <GND>
da_data[6] <= <GND>
da_data[7] <= <GND>
da_ldac_n <= <GND>
da_wr_n <= <GND>
ad_convst_n <= <GND>
ad_sclk <= <GND>
ad_din <= <GND>
ad_dout => ~NO_FANOUT~
ad_rfs <= <GND>
ad_tfs <= <GND>
usb_addr[0] <= <GND>
usb_addr[1] <= <GND>
usb_addr[2] <= <GND>
usb_addr[3] <= <GND>
usb_addr[4] <= <GND>
usb_addr[5] <= <GND>
usb_addr[6] <= <GND>
usb_addr[7] <= <GND>
usb_data[0] <= usb_data~31
usb_data[1] <= usb_data~30
usb_data[2] <= usb_data~29
usb_data[3] <= usb_data~28
usb_data[4] <= usb_data~27
usb_data[5] <= usb_data~26
usb_data[6] <= usb_data~25
usb_data[7] <= usb_data~24
usb_data[8] <= usb_data~23
usb_data[9] <= usb_data~22
usb_data[10] <= usb_data~21
usb_data[11] <= usb_data~20
usb_data[12] <= usb_data~19
usb_data[13] <= usb_data~18
usb_data[14] <= usb_data~17
usb_data[15] <= usb_data~16
usb_int => ~NO_FANOUT~
usb_rdy => ~NO_FANOUT~
usb_rst_n <= <GND>
usb_cs_n <= <GND>
usb_rd_n <= <GND>
usb_wr_n <= <GND>


|secondwatch|fenpin:fenpin_inst
clock => clock~0.IN1
cout <= lpm_counter:lpm_counter_component.cout
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
q[10] <= lpm_counter:lpm_counter_component.q
q[11] <= lpm_counter:lpm_counter_component.q
q[12] <= lpm_counter:lpm_counter_component.q
q[13] <= lpm_counter:lpm_counter_component.q
q[14] <= lpm_counter:lpm_counter_component.q
q[15] <= lpm_counter:lpm_counter_component.q
q[16] <= lpm_counter:lpm_counter_component.q
q[17] <= lpm_counter:lpm_counter_component.q
q[18] <= lpm_counter:lpm_counter_component.q
q[19] <= lpm_counter:lpm_counter_component.q
q[20] <= lpm_counter:lpm_counter_component.q


|secondwatch|fenpin:fenpin_inst|lpm_counter:lpm_counter_component
clock => cntr_mdj:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
data[19] => ~NO_FANOUT~
data[20] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_mdj:auto_generated.q[0]
q[1] <= cntr_mdj:auto_generated.q[1]
q[2] <= cntr_mdj:auto_generated.q[2]
q[3] <= cntr_mdj:auto_generated.q[3]
q[4] <= cntr_mdj:auto_generated.q[4]
q[5] <= cntr_mdj:auto_generated.q[5]
q[6] <= cntr_mdj:auto_generated.q[6]
q[7] <= cntr_mdj:auto_generated.q[7]
q[8] <= cntr_mdj:auto_generated.q[8]
q[9] <= cntr_mdj:auto_generated.q[9]
q[10] <= cntr_mdj:auto_generated.q[10]
q[11] <= cntr_mdj:auto_generated.q[11]
q[12] <= cntr_mdj:auto_generated.q[12]
q[13] <= cntr_mdj:auto_generated.q[13]
q[14] <= cntr_mdj:auto_generated.q[14]
q[15] <= cntr_mdj:auto_generated.q[15]
q[16] <= cntr_mdj:auto_generated.q[16]
q[17] <= cntr_mdj:auto_generated.q[17]
q[18] <= cntr_mdj:auto_generated.q[18]
q[19] <= cntr_mdj:auto_generated.q[19]
q[20] <= cntr_mdj:auto_generated.q[20]
cout <= cntr_mdj:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|secondwatch|fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
clock => counter_cella17.CLK
clock => counter_cella18.CLK
clock => counter_cella19.CLK
clock => counter_cella20.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
q[17] <= counter_cella17.REGOUT
q[18] <= counter_cella18.REGOUT
q[19] <= counter_cella19.REGOUT
q[20] <= counter_cella20.REGOUT


|secondwatch|rlshifter:rlshifter_sl
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => q[3]~reg0.CLK
reset => q[2]~reg0.ACLR
reset => q[1]~reg0.ACLR
reset => q[0]~reg0.ACLR
reset => q[3]~reg0.ACLR
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|secondwatch|fpcount:fpcount_sl
clk => cout[6].CLK
clk => cout[5].CLK
clk => cout[4].CLK
clk => cout[3].CLK
clk => cout[2].CLK
clk => cout[1].CLK
clk => cout[0].CLK
clk => cp.CLK
clk => cout[7].CLK
reset => cout[6].ACLR
reset => cout[5].ACLR
reset => cout[4].ACLR
reset => cout[3].ACLR
reset => cout[2].ACLR
reset => cout[1].ACLR
reset => cout[0].ACLR
reset => cout[7].ACLR
reset => cp.ENA
clk_fp <= cp.DB_MAX_OUTPUT_PORT_TYPE


|secondwatch|mux:mux_sl
select[0] => Mux0.IN3
select[0] => Mux1.IN3
select[0] => Mux2.IN3
select[0] => Mux3.IN3
select[1] => Mux0.IN2
select[1] => Mux1.IN2
select[1] => Mux2.IN2
select[1] => Mux3.IN2
select[2] => Mux0.IN1
select[2] => Mux1.IN1
select[2] => Mux2.IN1
select[2] => Mux3.IN1
select[3] => Mux0.IN0
select[3] => Mux1.IN0
select[3] => Mux2.IN0
select[3] => Mux3.IN0
in1[0] => Mux3.IN4
in1[0] => Mux3.IN5
in1[0] => Mux3.IN6
in1[0] => Mux3.IN7
in1[0] => Mux3.IN8
in1[0] => Mux3.IN9
in1[0] => Mux3.IN10
in1[0] => Mux3.IN11
in1[0] => Mux3.IN12
in1[0] => Mux3.IN13
in1[0] => Mux3.IN14
in1[0] => Mux3.IN15
in1[0] => Mux3.IN16
in1[1] => Mux2.IN4
in1[1] => Mux2.IN5
in1[1] => Mux2.IN6
in1[1] => Mux2.IN7
in1[1] => Mux2.IN8
in1[1] => Mux2.IN9
in1[1] => Mux2.IN10
in1[1] => Mux2.IN11
in1[1] => Mux2.IN12
in1[1] => Mux2.IN13
in1[1] => Mux2.IN14
in1[1] => Mux2.IN15
in1[1] => Mux2.IN16
in1[2] => Mux1.IN4
in1[2] => Mux1.IN5
in1[2] => Mux1.IN6
in1[2] => Mux1.IN7
in1[2] => Mux1.IN8
in1[2] => Mux1.IN9
in1[2] => Mux1.IN10
in1[2] => Mux1.IN11
in1[2] => Mux1.IN12
in1[2] => Mux1.IN13
in1[2] => Mux1.IN14
in1[2] => Mux1.IN15
in1[2] => Mux1.IN16
in1[3] => Mux0.IN4
in1[3] => Mux0.IN5
in1[3] => Mux0.IN6
in1[3] => Mux0.IN7
in1[3] => Mux0.IN8
in1[3] => Mux0.IN9
in1[3] => Mux0.IN10
in1[3] => Mux0.IN11
in1[3] => Mux0.IN12
in1[3] => Mux0.IN13
in1[3] => Mux0.IN14
in1[3] => Mux0.IN15
in1[3] => Mux0.IN16
in2[0] => Mux3.IN17
in2[1] => Mux2.IN17
in2[2] => Mux1.IN17
in2[3] => Mux0.IN17
in3[0] => Mux3.IN18
in3[1] => Mux2.IN18
in3[2] => Mux1.IN18
in3[3] => Mux0.IN18
in4[0] => Mux3.IN19
in4[1] => Mux2.IN19
in4[2] => Mux1.IN19
in4[3] => Mux0.IN19
out[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|secondwatch|decode4_7:decode4_7_sl
seg[0] <= seg[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= seg[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= seg[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= seg[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= seg[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= seg[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= seg[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Mux0.IN19
data[0] => Mux1.IN19
data[0] => Mux2.IN19
data[0] => Mux3.IN19
data[0] => Mux4.IN19
data[0] => Mux5.IN19
data[0] => Mux6.IN19
data[0] => Mux7.IN19
data[1] => Mux0.IN18
data[1] => Mux1.IN18
data[1] => Mux2.IN18
data[1] => Mux3.IN18
data[1] => Mux4.IN18
data[1] => Mux5.IN18
data[1] => Mux6.IN18
data[1] => Mux7.IN18
data[2] => Mux0.IN17
data[2] => Mux1.IN17
data[2] => Mux2.IN17
data[2] => Mux3.IN17
data[2] => Mux4.IN17
data[2] => Mux5.IN17
data[2] => Mux6.IN17
data[2] => Mux7.IN17
data[3] => Mux0.IN16
data[3] => Mux1.IN16
data[3] => Mux2.IN16
data[3] => Mux3.IN16
data[3] => Mux4.IN16
data[3] => Mux5.IN16
data[3] => Mux6.IN16
data[3] => Mux7.IN16


|secondwatch|jscount:jscount_sl
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[15].CLK
reset => count[14].ACLR
reset => count[13].ACLR
reset => count[12].ACLR
reset => count[11].ACLR
reset => count[10].ACLR
reset => count[9].ACLR
reset => count[8].ACLR
reset => count[7].ACLR
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[15].ACLR
out1[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
out1[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
out1[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
out1[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
out2[0] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
out2[1] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
out2[2] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
out2[3] <= count[7].DB_MAX_OUTPUT_PORT_TYPE
out3[0] <= count[8].DB_MAX_OUTPUT_PORT_TYPE
out3[1] <= count[9].DB_MAX_OUTPUT_PORT_TYPE
out3[2] <= count[10].DB_MAX_OUTPUT_PORT_TYPE
out3[3] <= count[11].DB_MAX_OUTPUT_PORT_TYPE
out4[0] <= count[12].DB_MAX_OUTPUT_PORT_TYPE
out4[1] <= count[13].DB_MAX_OUTPUT_PORT_TYPE
out4[2] <= count[14].DB_MAX_OUTPUT_PORT_TYPE
out4[3] <= count[15].DB_MAX_OUTPUT_PORT_TYPE