secondwatch.map.qmsg

用VERILOG实现的秒表 用VERILOG实现的秒表

{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "usb_rst_n TOP_FD_III.v(67) " "Warning (10034): Output port \"usb_rst_n\" at TOP_FD_III.v(67) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 67 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "usb_cs_n TOP_FD_III.v(68) " "Warning (10034): Output port \"usb_cs_n\" at TOP_FD_III.v(68) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 68 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "usb_rd_n TOP_FD_III.v(69) " "Warning (10034): Output port \"usb_rd_n\" at TOP_FD_III.v(69) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 69 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "usb_wr_n TOP_FD_III.v(72) " "Warning (10034): Output port \"usb_wr_n\" at TOP_FD_III.v(72) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 72 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fenpin.v 1 1 " "Warning: Using design file fenpin.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.v" "" { Text "D:/MYPROGRAM/secondwatch/fenpin.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:fenpin_inst " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:fenpin_inst\"" {  } { { "TOP_FD_III.v" "fenpin_inst" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 99 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 247 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter fenpin:fenpin_inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"fenpin:fenpin_inst\|lpm_counter:lpm_counter_component\"" {  } { { "fenpin.v" "lpm_counter_component" { Text "D:/MYPROGRAM/secondwatch/fenpin.v" 68 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fenpin:fenpin_inst\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"fenpin:fenpin_inst\|lpm_counter:lpm_counter_component\"" {  } { { "fenpin.v" "" { Text "D:/MYPROGRAM/secondwatch/fenpin.v" 68 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_mdj.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_mdj.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_mdj " "Info: Found entity 1: cntr_mdj" {  } { { "db/cntr_mdj.tdf" "" { Text "D:/MYPROGRAM/secondwatch/db/cntr_mdj.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_mdj fenpin:fenpin_inst\|lpm_counter:lpm_counter_component\|cntr_mdj:auto_generated " "Info: Elaborating entity \"cntr_mdj\" for hierarchy \"fenpin:fenpin_inst\|lpm_counter:lpm_counter_component\|cntr_mdj:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 271 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rlshifter rlshifter:rlshifter_sl " "Info: Elaborating entity \"rlshifter\" for hierarchy \"rlshifter:rlshifter_sl\"" {  } { { "TOP_FD_III.v" "rlshifter_sl" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 107 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fpcount fpcount:fpcount_sl " "Info: Elaborating entity \"fpcount\" for hierarchy \"fpcount:fpcount_sl\"" {  } { { "TOP_FD_III.v" "fpcount_sl" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 117 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 8count.v(18) " "Warning (10230): Verilog HDL assignment warning at 8count.v(18): truncated value with size 32 to match size of target (8)" {  } { { "8count.v" "" { Text "D:/MYPROGRAM/secondwatch/8count.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 8count.v(23) " "Warning (10230): Verilog HDL assignment warning at 8count.v(23): truncated value with size 32 to match size of target (8)" {  } { { "8count.v" "" { Text "D:/MYPROGRAM/secondwatch/8count.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux mux:mux_sl " "Info: Elaborating entity \"mux\" for hierarchy \"mux:mux_sl\"" {  } { { "TOP_FD_III.v" "mux_sl" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 128 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "4mux.v(9) " "Info (10264): Verilog HDL Case Statement information at 4mux.v(9): all case item expressions in this case statement are onehot" {  } { { "4mux.v" "" { Text "D:/MYPROGRAM/secondwatch/4mux.v" 9 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode4_7 decode4_7:decode4_7_sl " "Info: Elaborating entity \"decode4_7\" for hierarchy \"decode4_7:decode4_7_sl\"" {  } { { "TOP_FD_III.v" "decode4_7_sl" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 134 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "7seg.v(9) " "Warning (10270): Verilog HDL Case Statement warning at 7seg.v(9): incomplete case statement has no default case item" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "seg 7seg.v(7) " "Warning (10240): Verilog HDL Always Construct warning at 7seg.v(7): inferring latch(es) for variable \"seg\", which holds its previous value in one or more paths through the always construct" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 7 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[6\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[6\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[5\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[5\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[4\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[4\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[3\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[3\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[2\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[2\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[1\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[1\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "seg\[0\] 7seg.v(9) " "Info (10041): Verilog HDL or VHDL info at 7seg.v(9): inferred latch for \"seg\[0\]\"" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 9 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jscount jscount:jscount_sl " "Info: Elaborating entity \"jscount\" for hierarchy \"jscount:jscount_sl\"" {  } { { "TOP_FD_III.v" "jscount_sl" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 144 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}