secondwatch.map.qmsg

用VERILOG实现的秒表 用VERILOG实现的秒表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 14 12:38:24 2008 " "Info: Processing started: Sat Jun 14 12:38:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off secondwatch -c secondwatch " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off secondwatch -c secondwatch" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "16count2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file 16count2.v" { { "Info" "ISGN_ENTITY_NAME" "1 jscount " "Info: Found entity 1: jscount" {  } { { "16count2.v" "" { Text "D:/MYPROGRAM/secondwatch/16count2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "mux D:/MYPROGRAM/secondwatch/4mux.v " "Warning: Entity \"mux\" obtained from \"D:/MYPROGRAM/secondwatch/4mux.v\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "4mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file 4mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux " "Info: Found entity 1: mux" {  } { { "4mux.v" "" { Text "D:/MYPROGRAM/secondwatch/4mux.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file 7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode4_7 " "Info: Found entity 1: decode4_7" {  } { { "7seg.v" "" { Text "D:/MYPROGRAM/secondwatch/7seg.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "8count.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file 8count.v" { { "Info" "ISGN_ENTITY_NAME" "1 fpcount " "Info: Found entity 1: fpcount" {  } { { "8count.v" "" { Text "D:/MYPROGRAM/secondwatch/8count.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rlshifter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rlshifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 rlshifter " "Info: Found entity 1: rlshifter" {  } { { "rlshifter.v" "" { Text "D:/MYPROGRAM/secondwatch/rlshifter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "sel_sram TOP_FD_III.v(82) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(82): created implicit net for \"sel_sram\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 82 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "clk1 TOP_FD_III.v(97) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(97): created implicit net for \"clk1\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 97 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "clk2 TOP_FD_III.v(116) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(116): created implicit net for \"clk2\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 116 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "first TOP_FD_III.v(123) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(123): created implicit net for \"first\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 123 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "second TOP_FD_III.v(124) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(124): created implicit net for \"second\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 124 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "third TOP_FD_III.v(125) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(125): created implicit net for \"third\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 125 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "fouth TOP_FD_III.v(126) " "Warning (10236): Verilog HDL Implicit Net warning at TOP_FD_III.v(126): created implicit net for \"fouth\"" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 126 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TOP_FD_III.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file TOP_FD_III.v" { { "Info" "ISGN_ENTITY_NAME" "1 secondwatch " "Info: Found entity 1: secondwatch" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "secondwatch " "Info: Elaborating entity \"secondwatch\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "sel_sram TOP_FD_III.v(82) " "Warning (10036): Verilog HDL or VHDL warning at TOP_FD_III.v(82): object \"sel_sram\" assigned a value but never read" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[20\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[20\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[19\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[19\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[18\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[18\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[17\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[17\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[16\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[16\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[15\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[15\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[14\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[14\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[13\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[13\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "mem_addr\[12\] TOP_FD_III.v(16) " "Warning (10034): Output port \"mem_addr\[12\]\" at TOP_FD_III.v(16) has no driver" {  } { { "TOP_FD_III.v" "" { Text "D:/MYPROGRAM/secondwatch/TOP_FD_III.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}