secondwatch.fit.smsg

用VERILOG实现的秒表 用VERILOG实现的秒表

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Jun 14 12:38:30 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off secondwatch -c secondwatch
Info: Selected device EP1C6Q240C8 for design "secondwatch"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 196 of 196 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clkin" to use Global clock in PIN 28
Info: Automatically promoted some destinations of signal "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|modulus_trigger" to use Global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella0" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella1" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella2" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella3" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella4" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella5" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella6" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella7" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella11" may be non-global or may not use global clock
    Info: Destination "fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|counter_cella8" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Automatically promoted signal "fpcount:fpcount_sl|cp" to use Global clock
Info: Automatically promoted some destinations of signal "reset_n" to use Global clock
    Info: Destination "fpcount:fpcount_sl|cp" may be non-global or may not use global clock
Info: Pin "reset_n" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 7.205 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y6; Fanout = 3; REG Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15]'
    Info: 2: + IC(1.315 ns) + CELL(0.114 ns) = 1.429 ns; Loc. = LAB_X7_Y4; Fanout = 1; COMB Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|cmpr1_aeb_int~165'
    Info: 3: + IC(1.251 ns) + CELL(0.114 ns) = 2.794 ns; Loc. = LAB_X7_Y7; Fanout = 1; COMB Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|cmpr1_aeb_int~166'
    Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 3.447 ns; Loc. = LAB_X7_Y7; Fanout = 1; COMB Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|cmpr1_aeb_int~0'
    Info: 5: + IC(0.964 ns) + CELL(0.442 ns) = 4.853 ns; Loc. = LAB_X7_Y5; Fanout = 30; COMB Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|modulus_trigger'
    Info: 6: + IC(1.127 ns) + CELL(1.225 ns) = 7.205 ns; Loc. = LAB_X7_Y7; Fanout = 3; REG Node = 'fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[0]'
    Info: Total cell delay = 2.485 ns ( 34.49 % )
    Info: Total interconnect delay = 4.720 ns ( 65.51 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X11_Y10
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
    Info: Pin mem_data[0] has a permanently disabled output enable
    Info: Pin mem_data[1] has a permanently disabled output enable
    Info: Pin mem_data[2] has a permanently disabled output enable
    Info: Pin mem_data[3] has a permanently disabled output enable
    Info: Pin mem_data[4] has a permanently disabled output enable
    Info: Pin mem_data[5] has a permanently disabled output enable
    Info: Pin mem_data[6] has a permanently disabled output enable
    Info: Pin mem_data[7] has a permanently disabled output enable
    Info: Pin mem_data[8] has a permanently disabled output enable
    Info: Pin mem_data[9] has a permanently disabled output enable
    Info: Pin mem_data[10] has a permanently disabled output enable
    Info: Pin mem_data[11] has a permanently disabled output enable
    Info: Pin mem_data[12] has a permanently disabled output enable
    Info: Pin mem_data[13] has a permanently disabled output enable
    Info: Pin mem_data[14] has a permanently disabled output enable
    Info: Pin mem_data[15] has a permanently disabled output enable
    Info: Pin lcd_data[0] has a permanently disabled output enable
    Info: Pin lcd_data[1] has a permanently disabled output enable
    Info: Pin lcd_data[2] has a permanently disabled output enable
    Info: Pin lcd_data[3] has a permanently disabled output enable
    Info: Pin lcd_data[4] has a permanently disabled output enable
    Info: Pin lcd_data[5] has a permanently disabled output enable
    Info: Pin lcd_data[6] has a permanently disabled output enable
    Info: Pin lcd_data[7] has a permanently disabled output enable
    Info: Pin usb_data[0] has a permanently disabled output enable
    Info: Pin usb_data[1] has a permanently disabled output enable
    Info: Pin usb_data[2] has a permanently disabled output enable
    Info: Pin usb_data[3] has a permanently disabled output enable
    Info: Pin usb_data[4] has a permanently disabled output enable
    Info: Pin usb_data[5] has a permanently disabled output enable
    Info: Pin usb_data[6] has a permanently disabled output enable
    Info: Pin usb_data[7] has a permanently disabled output enable
    Info: Pin usb_data[8] has a permanently disabled output enable
    Info: Pin usb_data[9] has a permanently disabled output enable
    Info: Pin usb_data[10] has a permanently disabled output enable
    Info: Pin usb_data[11] has a permanently disabled output enable
    Info: Pin usb_data[12] has a permanently disabled output enable
    Info: Pin usb_data[13] has a permanently disabled output enable
    Info: Pin usb_data[14] has a permanently disabled output enable
    Info: Pin usb_data[15] has a permanently disabled output enable
Warning: Following 127 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin mem_data[0] has VCC driving its datain port
    Info: Pin mem_data[1] has VCC driving its datain port
    Info: Pin mem_data[2] has VCC driving its datain port
    Info: Pin mem_data[3] has VCC driving its datain port
    Info: Pin mem_data[4] has VCC driving its datain port
    Info: Pin mem_data[5] has VCC driving its datain port
    Info: Pin mem_data[6] has VCC driving its datain port
    Info: Pin mem_data[7] has VCC driving its datain port
    Info: Pin mem_data[8] has VCC driving its datain port
    Info: Pin mem_data[9] has VCC driving its datain port
    Info: Pin mem_data[10] has VCC driving its datain port
    Info: Pin mem_data[11] has VCC driving its datain port
    Info: Pin mem_data[12] has VCC driving its datain port