16count.v.bak

用VERILOG实现的秒表 用VERILOG实现的秒表

module sixteencount(reset,clk,outf,outs,outt,outfo);
  
  input clk,reset;
  output[3:0] outf;
  output[3:0] outs;
  output[3:0] outt;
  output[3:0] outfo;
  reg[3:0] outf,outs,outt,outfo;
  
  integer cn1,cn2,cn3;

  always@(posedge clk or posedge reset)
    begin
     if (reset==1'b1)
       begin
        {outf,outs,outt,outfo}<=16'h0000;
         cn1<=0;
         cn2<=0;
         cn3<=0;
       end
     else if(outf<10)
       begin
        outf<=outf+1;
        cn1<=0;
       end
     else if(outf==4'b1010)
       begin
         outf<=4'h0;
	     cn1<=1;
       end
     else outf=4'h0;
    end

  always@(posedge cn1)
    begin
      if (outs < 10)
        begin
	      outs<=outs+1;
	      cn2<=0;
	    end
      else  if (outs==4'b1010)
        begin
	     outs<=4'h0;
	     cn2<=1;
	    end
     end

 always@(posedge cn2)
   begin
     if (outt < 10)
	     begin
	     outt<=outt+1;
	     cn3<=0;
	     end
      else if (outt==4'b1010)
	     begin
	     outt<=4'h0;
	     cn3<=1;
	     end
    end

  always@(posedge cn3)
   begin
     if (outfo < 10)
	  outfo<=outfo+1;
      else if (outfo==4'b1010)
	  outfo<=4'h0;
    end
endmodule