i2c.v

清华大学verilog hdl源码例子

module i2c(     
				  addr,               // cpu address bus               
                rst_l,
                clock,                           
                i2c_rdata,	    
                scl_pin,            // i2c clock
                sda_pin);           // i2c data
                

//-------------------------------------------------------------------
// microprocessor interface

input   [1:0]   addr;               // cpu address bus
input           rst_l;              // async reset
input           clock;              // cpu clock
output	[7:0]	i2c_rdata;


//-------------------------------------------------------------------
// i2c interface

output          scl_pin;            // i2c clock
inout           sda_pin;            // i2c data
                 
//-------------------------------------------------------------------
// interconnect wires

// cpu interface wires

wire    [1:0]   addr;               // cpu address bus
wire            rst_l;              // async reset
wire            clock;              // cpu clock

wire            ack_l;              // acknowledge out to cpu

// i2c interface wires

wire            scl_pin;
wire            sda_pin;

// clock output wires
wire            scl_tick;           // 5 usec clock tick

// state machine wires

wire    [7:0]   i2c_rdata;          // i2c read data        

wire            sda;                // i2c data
wire            scl;                // i2c clock

//-------------------------------------------------------------------


// module instantiations

// i2c clock
i2c_clk U3(     .rst_l(rst_l),
                .clock(clock),
                .scl_cnt_en(scl_cnt_en),
                .scl_tick(scl_tick));                

// i2c state machine

i2c_st U4(      .rst_l(rst_l),
                .clock(clock),
                .scl_tick(scl_tick),
                .sda_pin(sda_pin),
                .sda(sda),
                .scl(scl),
                .scl_cnt_en(scl_cnt_en),            
                .i2c_rdata(i2c_rdata));

assign scl_pin = scl ? 1'bz : 1'b0;
assign sda_pin = sda ? 1'bz : 1'b0;
                


endmodule