16_multi.v

来自「16*16有符号乘法器的 &#61548 编码方式：Booth编码」· Verilog 代码 · 共 141 行

//--------------------------------------------------------------------
//
//      Design          :    16_multiplier
//
//      File name       :       16_multiplier.v
//
//      Purpose         :       
//
//      Limitations     :       
//
//      Errors          :       None known
//
//      Include files   :       None
//
//      Author          :       Chen Yi, Dec 30, 2007
//
//      Simulator       :       ModelSim SE 6.1
//
//--------------------------------------------------------------------
//      Revision List
//      Version         Author          Date            Change
//                                                      
//      0.1              Chen Yi       07/12/30       
//--------------------------------------------------------------------
module booth(clk, reset, load, A, B, done, result);

  parameter WidthMultiplicand = 16,

                   WidthMultiplier = 16,

                   WidthCount = 5,

Comp_add = 3'b010,

Add = 3'b001;

 

  input clk, reset, load;

  input [WidthMultiplicand-1:0] A;

  input [WidthMultiplier-1:0] B;

  output [WidthMultiplicand+WidthMultiplier-1:0] result;

  output done; 

  reg done, sign, E, shift, Qn_1;

  reg [WidthMultiplicand-1:0] regA;

  reg [WidthMultiplier-1:0] regB, regQ;

  reg [WidthCount-1:0] SeqCount;

  assign result = {regA,regQ};

 

  always @(posedge clk) begin

    if(!reset) begin

      regA = 0;

      regB = 0;

      regQ = 0;

      Qn_1 = 0;

      shift = 0;

      SeqCount = WidthMultiplier;

      done = 0;

    end

    else if (load) begin

      regA = 0;

      regB = A;

      regQ = B;

      Qn_1 = 0;

      shift = 0;

      SeqCount = WidthMultiplier;

      done = 0;

    end

    else if (!done) 

      case({shift,regQ[0],Qn_1})

        Comp_add:begin

          regA = regA + ~regB + 1;

          shift = 1;

          end

        Add:begin

          regA = regA + regB;

          shift = 1;

          end

          default:begin

            {regA,regQ,Qn_1} = ({regA,regQ,Qn_1}>>1);

            regA[WidthMultiplicand-1] = regA[WidthMultiplicand-2];

            SeqCount = SeqCount - 1;

            shift = 0;

            if (SeqCount == 0)

              done = 1;

          end

      endcase    

 

  end

endmodule