test_multi.v

来自「16*16有符号乘法器的 &#61548 编码方式：Booth编码」· Verilog 代码 · 共 53 行

`timescale 	 1ns/1ns



module test_booth;


reg [15:0] A;
reg [15:0] B;
reg clk;
reg reset;
reg load;


wire [31:0] result;
wire done;


booth booth(
   .clk      (clk),
   .reset    (reset),
   .load     (load),
   .A        (A),
   .B        (B),
   .done     (done),
   .result   (result)
   );



initial  
    begin
       clk = 0;
       reset=1;
    
       load = 1;
       
       A[15:0] = 16'b1111111111111101;
       B[15:0] = 16'b0000000001011010;
    end

always
#32 clk = ~clk;
always
  begin
#128 load = 0;
#4096 load = 1;

end

endmodule