_primary.vhd

来自「16*16有符号乘法器的 &#61548 编码方式：Booth编码」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity mul is
    generic(
        WidthMultiplicand: integer := 16;
        WidthMultiplier : integer := 16;
        WidthCount      : integer := 5
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        load            : in     vl_logic;
        A               : in     vl_logic_vector;
        B               : in     vl_logic_vector;
        done            : out    vl_logic;
        result          : out    vl_logic_vector
    );
end mul;