16_multi.v.bak

16*16有符号乘法器的 &#61548 编码方式：Booth编码

//--------------------------------------------------------------------
//
//      Design          :    16_multiplier
//
//      File name       :       16_multiplier.v
//
//      Purpose         :       
//
//      Limitations     :       
//
//      Errors          :       None known
//
//      Include files   :       None
//
//      Author          :       Chen Yi, Dec 30, 2007
//
//      Simulator       :       ModelSim SE 6.1
//
//--------------------------------------------------------------------
//      Revision List
//      Version         Author          Date            Change
//                                                      
//      0.1              Chen Yi       07/12/30       
//--------------------------------------------------------------------
module mul(clk, reset, load, A, B, done, result);

  parameter WidthMultiplicand = 16,

            WidthMultiplier = 16,

            WidthCount = 5;

  

  input clk, reset, load;

  input [WidthMultiplicand-1:0] A;

  input [WidthMultiplier-1:0] B;

  

  output done;

  output [WidthMultiplicand+WidthMultiplier-1:0] result;

  

  reg done, sign, E, add_shiftb;

  reg [WidthMultiplicand-2:0] reg1,reg2;

  reg [WidthMultiplier-2:0] regQ;  

  reg [WidthCount-1:0] SeqCount;

 

  wire [WidthMultiplicand+WidthMultiplier-2:0] w_result;

  assign result = {sign,reg1,regQ};

 

  always @(posedge clk) begin

    if (!reset) begin

      sign = 0;

      reg1 = 0;

      reg2 = 0;

      regQ = 0;

      E = 0;

      add_shiftb = 0;

      SeqCount = WidthMultiplier-2;

      done = 0;

    end

    else if (load) begin

      sign = A[WidthMultiplicand-1] ^ B[WidthMultiplier-1];

      reg1 = 0;

      reg2 = A[WidthMultiplicand-2:0];

      regQ = B[WidthMultiplier-2:0];

      E=0;

      add_shiftb = B[0];

      SeqCount = WidthMultiplier-2;

      done = 0;

    end

    else if (add_shiftb) begin

      {E,reg1} = reg2 + reg1;

      add_shiftb = 0;

    end

    else if (!done) begin

      {E,reg1,regQ} = {E,reg1,regQ} >> 1;

      if (regQ[0])

        add_shiftb = 1;

      else

        add_shiftb = 0;

      if (SeqCount == 0)

        done = 1;

      else SeqCount = SeqCount-1;

    end

  end

endmodule