adder8.tan.qmsg

8位加法器的实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 08 16:35:24 2008 " "Info: Processing started: Thu May 08 16:35:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder8 -c adder8 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder8 -c adder8 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B\[0\] SUM\[7\] 9.542 ns Longest " "Info: Longest tpd from source pin \"B\[0\]\" to destination pin \"SUM\[7\]\" is 9.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns B\[0\] 1 PIN PIN_V24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_V24; Fanout = 3; PIN Node = 'B\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { B[0] } "NODE_NAME" } } { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 32 16 184 48 "B\[3..0\]" "" } { 48 16 184 64 "B\[7..4\]" "" } { 192 150 176 208 "B\[0\]" "" } { 224 152 176 240 "B\[1\]" "" } { 256 152 176 272 "B\[2\]" "" } { 288 152 180 304 "B\[3\]" "" } { 192 392 420 208 "B\[4\]" "" } { 224 392 420 240 "B\[5\]" "" } { 256 392 420 272 "B\[6\]" "" } { 288 392 420 304 "B\[7\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.770 ns) + CELL(0.366 ns) 4.966 ns 74283:inst\|f74283:sub\|105~76 2 COMB LCCOMB_X1_Y5_N24 3 " "Info: 2: + IC(3.770 ns) + CELL(0.366 ns) = 4.966 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 3; COMB Node = '74283:inst\|f74283:sub\|105~76'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.136 ns" { B[0] 74283:inst|f74283:sub|105~76 } "NODE_NAME" } } { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { { 416 408 472 456 "105" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.053 ns) 5.489 ns 74283:inst\|f74283:sub\|107~169 3 COMB LCCOMB_X1_Y5_N10 3 " "Info: 3: + IC(0.470 ns) + CELL(0.053 ns) = 5.489 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 3; COMB Node = '74283:inst\|f74283:sub\|107~169'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.523 ns" { 74283:inst|f74283:sub|105~76 74283:inst|f74283:sub|107~169 } "NODE_NAME" } } { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { { 904 408 472 944 "107" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.346 ns) 6.091 ns 74283:inst1\|f74283:sub\|105~51 4 COMB LCCOMB_X1_Y5_N16 3 " "Info: 4: + IC(0.256 ns) + CELL(0.346 ns) = 6.091 ns; Loc. = LCCOMB_X1_Y5_N16; Fanout = 3; COMB Node = '74283:inst1\|f74283:sub\|105~51'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.602 ns" { 74283:inst|f74283:sub|107~169 74283:inst1|f74283:sub|105~51 } "NODE_NAME" } } { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { { 416 408 472 456 "105" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.366 ns) 6.742 ns 74283:inst1\|f74283:sub\|82 5 COMB LCCOMB_X1_Y5_N12 1 " "Info: 5: + IC(0.285 ns) + CELL(0.366 ns) = 6.742 ns; Loc. = LCCOMB_X1_Y5_N12; Fanout = 1; COMB Node = '74283:inst1\|f74283:sub\|82'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.651 ns" { 74283:inst1|f74283:sub|105~51 74283:inst1|f74283:sub|82 } "NODE_NAME" } } { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { { 816 600 664 856 "82" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(2.164 ns) 9.542 ns SUM\[7\] 6 PIN PIN_U25 0 " "Info: 6: + IC(0.636 ns) + CELL(2.164 ns) = 9.542 ns; Loc. = PIN_U25; Fanout = 0; PIN Node = 'SUM\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { 74283:inst1|f74283:sub|82 SUM[7] } "NODE_NAME" } } { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 48 352 528 64 "SUM\[7..4\]" "" } { 0 352 528 16 "SUM\[3..0\]" "" } { 192 280 324 208 "SUM\[0\]" "" } { 208 280 324 224 "SUM\[1\]" "" } { 224 280 324 240 "SUM\[2\]" "" } { 240 280 324 256 "SUM\[3\]" "" } { 192 512 556 208 "SUM\[4\]" "" } { 208 512 556 224 "SUM\[5\]" "" } { 224 512 556 240 "SUM\[6\]" "" } { 240 512 556 256 "SUM\[7\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.125 ns ( 43.23 % ) " "Info: Total cell delay = 4.125 ns ( 43.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.417 ns ( 56.77 % ) " "Info: Total interconnect delay = 5.417 ns ( 56.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.542 ns" { B[0] 74283:inst|f74283:sub|105~76 74283:inst|f74283:sub|107~169 74283:inst1|f74283:sub|105~51 74283:inst1|f74283:sub|82 SUM[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.542 ns" { B[0] {} B[0]~combout {} 74283:inst|f74283:sub|105~76 {} 74283:inst|f74283:sub|107~169 {} 74283:inst1|f74283:sub|105~51 {} 74283:inst1|f74283:sub|82 {} SUM[7] {} } { 0.000ns 0.000ns 3.770ns 0.470ns 0.256ns 0.285ns 0.636ns } { 0.000ns 0.830ns 0.366ns 0.053ns 0.346ns 0.366ns 2.164ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 08 16:35:25 2008 " "Info: Processing ended: Thu May 08 16:35:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}