adder8.map.qmsg

8位加法器的实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 08 16:34:58 2008 " "Info: Processing started: Thu May 08 16:34:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder8.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder8.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder8 " "Info: Found entity 1: adder8" {  } { { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder8 " "Info: Elaborating entity \"adder8\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/others/maxplus2/74283.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/others/maxplus2/74283.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 74283 " "Info: Found entity 1: 74283" {  } { { "74283.tdf" "" { Text "d:/altera/72/quartus/libraries/others/maxplus2/74283.tdf" 13 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74283 74283:inst1 " "Info: Elaborating entity \"74283\" for hierarchy \"74283:inst1\"" {  } { { "adder8.bdf" "inst1" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 152 408 512 328 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74283:inst1 " "Info: Elaborated megafunction instantiation \"74283:inst1\"" {  } { { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 152 408 512 328 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 f74283 " "Info: Found entity 1: f74283" {  } { { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f74283 74283:inst1\|f74283:sub " "Info: Elaborating entity \"f74283\" for hierarchy \"74283:inst1\|f74283:sub\"" {  } { { "74283.tdf" "sub" { Text "d:/altera/72/quartus/libraries/others/maxplus2/74283.tdf" 24 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "f74283 " "Warning: Processing legacy GDF or BDF entity \"f74283\" with Max+Plus II bus and instance naming rules" {  } { { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WGDFX_MIXED_DESIGN_FILE_NAMING" "" "Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." {  } { { "f74283.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/f74283.bdf" { } } }  } 0 0 "The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "74283:inst1\|f74283:sub 74283:inst1 " "Info: Elaborated megafunction instantiation \"74283:inst1\|f74283:sub\", which is child of megafunction instantiation \"74283:inst1\"" {  } { { "74283.tdf" "" { Text "d:/altera/72/quartus/libraries/others/maxplus2/74283.tdf" 24 3 0 } } { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 152 408 512 328 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74283 74283:inst " "Info: Elaborating entity \"74283\" for hierarchy \"74283:inst\"" {  } { { "adder8.bdf" "inst" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 152 176 280 328 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74283:inst " "Info: Elaborated megafunction instantiation \"74283:inst\"" {  } { { "adder8.bdf" "" { Schematic "e:/fpga/ex/bdf/adder8.bdf" { { 152 176 280 328 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "31 " "Info: Ignored 31 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_CARRY" "9 " "Info: Ignored 9 CARRY buffer(s)" {  } {  } 0 0 "Ignored %1!d! CARRY buffer(s)" 0 0 "" 0} { "Info" "IOPT_MLS_IGNORED_SOFT" "22 " "Info: Ignored 22 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Info: Implemented 16 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 08 16:35:00 2008 " "Info: Processing ended: Thu May 08 16:35:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}