main.tan.summary

这是一个用verilog语言设计的数字频率及的源代码

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 82.300 ns
From           : flip_latch:inst2|Q5[2]
To             : disp_data[5]
From Clock     : Clock
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 21.000 ns
From           : SW0
To             : disp_data[5]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'Clock'
Slack          : N/A
Required Time  : None
Actual Time    : 17.12 MHz ( period = 58.400 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : Clock
To Clock       : Clock
Failed Paths   : 0

Type           : Clock Setup: 'SW1'
Slack          : N/A
Required Time  : None
Actual Time    : 23.15 MHz ( period = 43.200 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW2'
Slack          : N/A
Required Time  : None
Actual Time    : 33.56 MHz ( period = 29.800 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 0

Type           : Clock Setup: 'SW0'
Slack          : N/A
Required Time  : None
Actual Time    : 41.32 MHz ( period = 24.200 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW0
To Clock       : SW0
Failed Paths   : 0

Type           : Clock Setup: 'F_in'
Slack          : N/A
Required Time  : None
Actual Time    : 53.48 MHz ( period = 18.700 ns )
From           : counter:inst|lpm_counter:Q1_rtl_2|dffs[1]
To             : counter:inst|lpm_counter:Q3_rtl_4|dffs[0]
From Clock     : F_in
To Clock       : F_in
Failed Paths   : 0

Type           : Clock Hold: 'Clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : Clock
To Clock       : Clock
Failed Paths   : 2

Type           : Clock Hold: 'SW1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 2

Type           : Clock Hold: 'SW2'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 2

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 6

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