rs_inner_buffer.v

rs的译码器

                                                        
//                                                                                          
//Design       : Reed-Solomon decoder RS(204,188) in QAM                                    
//                                                                                          
//File Name    : rs_inner_buffer.v                                                          
//                                                                                          
//Perpose      : compute the error value at each locator                                    
//                                                                                          
    
                                                                                            
//synopsys translate_off                                                                    
`include  "timescale.v"                                                                     
//synopsys translate_on

module rs_inner_buffer ( clk              ,
                         phase1           ,
                         clken            ,
                         n_rst            ,
                         data_in_start    ,
                         data_in_valid    ,
                         data_in          ,
                         addr_latch       ,
                         data_out
                        );

//ports declaration
input                    clk              ;
input                    phase1           ;
input                    clken            ;
input                    n_rst            ;
input                    data_in_start    ;
input                    data_in_valid    ;
input  [7:0]             data_in          ;
output [8:0]             addr_latch       ;
output [7:0]             data_out         ;

//Infer the local regs
reg    [1:0]             phase_counter    ;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      phase_counter <= 2'h0;
    else if ( phase1 == 1'b1 && clk == 1'b1 )
      phase_counter <= 2'h0;
    else if ( clken == 1'b1 )
      phase_counter <= phase_counter + 1;
    else;
  end

reg    [7:0]             symbol_latch     ;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 ) 
      symbol_latch <= 8'h0 ;
    else if ( data_in_valid == 1'b1 && clken == 1'b1 && phase1 == 1'b1 )
      symbol_latch <= data_in ;
    else if ( clken == 1'b1 && phase1 == 1'b1 )
      symbol_latch <= 8'h0 ;
    else;
  end        

reg    [8:0]             waddr ;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      waddr <= 9'h0;
    else if( data_in_valid == 1'b0 && clken == 1'b1 && phase1 == 1'b1 )
      waddr <= 9'h0;
    else if( data_in_start == 1'b0 && waddr == 9'h0 && clken == 1'b1 && phase1 == 1'b1 )
      waddr <= 9'h0; 
    else if( data_in_start == 1'b0 && waddr == 9'hd0 && clken == 1'b1 && phase1 == 1'b1 )
      waddr <= 9'hd0;
    else if( waddr == 9'hcb && clken == 1'b1 && phase1 == 1'b1 )
      waddr <= 9'hd0;
    else if( waddr == 9'h19b && clken == 1'b1 && phase1 == 1'b1 )
      waddr <= 9'h0;
    else if( clken == 1'b1 && phase1 == 1'b1 )
      waddr <= waddr + 1'b1;
    else;
  end

reg    [8:0]             raddr ;
always@( posedge clk or negedge n_rst ) 
  begin
    if ( n_rst == 1'b0 )
      raddr <= 9'h0;
    else if( data_in_valid == 1'b0 && clken == 1'b1 && phase1 == 1'b1 )
      raddr <= 9'h0;
    else if( waddr == 9'hca && clken == 1'b1 && phase_counter == 2'b01 )
      raddr <= 9'hd0;
    else if( waddr == 9'hcb && clken == 1'b1 && phase_counter == 2'b01 )
      raddr <= 9'hd1;
    else if( waddr == 9'h19a && clken == 1'b1 && phase_counter == 2'b01 )
      raddr <= 9'h0;
    else if( waddr == 9'h19b && clken == 1'b1 && phase_counter == 2'b01 )
      raddr <= 9'h1;
    else if( clken == 1'b1 && phase_counter == 2'b01 )
      raddr <= waddr + 2;  
    else;  
  end  
    
wire  [8:0]              addr;
assign                   addr = ( phase_counter == 2'b00 || phase_counter == 2'b01 ) ? waddr : raddr ;

reg   [8:0]              addr_latch;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      addr_latch <= 9'h0;
    else if ( clken == 1'b1 )
      addr_latch <= addr;
    else;
  end

reg                      we;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      we <= 1'b0 ;
    else if ( phase_counter == 2'h0 && clken == 1'b1 )
      we <= 1'b1 ;
    else if ( phase_counter == 2'h2 && clken == 1'b1 )
      we <= 1'b0 ;
    else;
  end

reg                      CEN;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      CEN <= 1'b1 ;
    else if ( ( phase_counter == 2'h0 || phase_counter == 2'h2 ) && clken == 1'b1 )
      CEN <= 1'b0 ;
    else if ( clken == 1'b1 )
      CEN <= 1'b1 ;
    else;
  end    

reg                      clk_div; 
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      clk_div <= 1'b1 ;
    else if ( clken == 1'b1 )
      clk_div <= ~ clk_div ; 
    else;
  end  

//For FPGA simulation

rs_inner_buf         rs_inner_buf
                  ( .q        (data_out  ),
                    .data     (data_in   ),
                    .inclock  (clk_div   ),
                    .outclock (1'b1      ),
                    .we       (we        ),
                    .address  (addr_latch)
                   );

//            defparam lpm_type = "lpm_ram_dq";
//            defparam lpm_width = 8;
//            defparam lpm_widthad = 9;
//            defparam lpm_indata = "REGISTERED";
//            defparam lpm_address_control = "REGISTERED";
//            defparam lpm_outdata = "UNREGISTERED";
//            defparam lpm_file = "UNUSED";
//            defparam lpm_hint = "UNUSED";
//            defparam use_eab = "OFF";
//            defparam intended_device_family = "UNUSED";

//For FPGA synthesis
//rs_inner_buf         rs_inner_buf          
//                  ( .q        (data_out  ),
//                    .data     (data_in   ),
//                    .clock    (clk_div   ),
//                    .wren     (we        ),
//                    .address  (addr_latch) 
//                   );                   

//For ASIC simulation and synthesis
//rs_inner_buf          rs_inner_buf
//                   ( .DOUT (data_out  ),
//                     .AD   (addr_latch),
//                     .CEN  (1'b0      ),
//                     .CLK  (clk_div   ),
//                     .DIN  (data_in   ),
//                     .OE   (1'b1      ),
//                     .WE   (we        )
//                    );

endmodule