mux2_1.v

来自「rs的译码器」· Verilog 代码 · 共 25 行

                
//                                                                               
//Design       : Reed-Solomon decoder RS(204,188) in QAM                         
//                                                                               
//File Name    : mux2_1.v                                                      
//                                                                               
//Perpose      : This is a multiplexer use to select a stream of data from 2               
//                                                       
//                                                                               
 
                                                                                 
//synopsys translate_off                                                         
`include  "timescale.v"                                                          
//synopsys translate_on

module mux2_1 ( a , b , sel , c );    
                                      
input  [7:0]      a, b;               
input             sel;                
output [7:0]      c;                                                                            
                                      
assign  c = ( sel == 1'b1 ) ?  a : b ;

endmodule