d_reg8_decoder.v

来自「rs的译码器」· Verilog 代码 · 共 44 行

                                                    
//                                                                               
//Design       : Reed-Solomon decoder RS(204,188) in QAM                         
//                                                                               
//File Name    : D_reg8_decoder.v                                             
//                                                                               
//Perpose      : D_reg8_decoder is a line of 8 D_flip_flops use to store the intermediate results       
//               in the RS decoder      
//                                                                                                          


//synopsys translate_off
`include  "timescale.v" 
//synopsys translate_on 

module D_reg8_decoder ( D,
                        q,
                        clk,
                        clken,
                        phase1,
                        n_rst
                        );

input  [7:0]    D;
input           clk;
input           clken;
input           phase1;
input           n_rst;
output [7:0]    q;

reg    [7:0]    q;

always@(posedge clk or negedge n_rst)
  begin
    if( n_rst == 1'b0 ) 
      q <= 8'h0;
    else if ( clken == 1'b1 && phase1 == 1'b1 )
      q <= D;   
    else
      q <= q;
  end

endmodule