📄 rs_204_188_dec_top.v
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.omega6 (omega6 ),
.omega5 (omega5 ),
.omega4 (omega4 ),
.omega3 (omega3 ),
.omega2 (omega2 ),
.omega1 (omega1 ),
.omega0 (omega0 ),
.syndrome15 (syndrome15 ),
.syndrome14 (syndrome14 ),
.syndrome13 (syndrome13 ),
.syndrome12 (syndrome12 ),
.syndrome11 (syndrome11 ),
.syndrome10 (syndrome10 ),
.syndrome9 (syndrome9 ),
.syndrome8 (syndrome8 ),
.syndrome7 (syndrome7 ),
.syndrome6 (syndrome6 ),
.syndrome5 (syndrome5 ),
.syndrome4 (syndrome4 ),
.syndrome3 (syndrome3 ),
.syndrome2 (syndrome2 ),
.syndrome1 (syndrome1 ),
.syndrome0 (syndrome0 )
);
chien_search chien_search
( .clk (clk ),
.n_rst (n_rst ),
.clken (clken ),
.phase1 (phase1 ),
.data_in_valid (MEA_out_valid ),
.data_in_start (MEA_out_start ),
.syndrome_zero_in (syndrome_zero_out_MEA ),
.omega_cof16 (omega16 ),
.omega_cof15 (omega15 ),
.omega_cof14 (omega14 ),
.omega_cof13 (omega13 ),
.omega_cof12 (omega12 ),
.omega_cof11 (omega11 ),
.omega_cof10 (omega10 ),
.omega_cof9 (omega9 ),
.omega_cof8 (omega8 ),
.omega_cof7 (omega7 ),
.omega_cof6 (omega6 ),
.omega_cof5 (omega5 ),
.omega_cof4 (omega4 ),
.omega_cof3 (omega3 ),
.omega_cof2 (omega2 ),
.omega_cof1 (omega1 ),
.omega_cof0 (omega0 ),
.delta_cof16 (delta16 ),
.delta_cof15 (delta15 ),
.delta_cof14 (delta14 ),
.delta_cof13 (delta13 ),
.delta_cof12 (delta12 ),
.delta_cof11 (delta11 ),
.delta_cof10 (delta10 ),
.delta_cof9 (delta9 ),
.delta_cof8 (delta8 ),
.delta_cof7 (delta7 ),
.delta_cof6 (delta6 ),
.delta_cof5 (delta5 ),
.delta_cof4 (delta4 ),
.delta_cof3 (delta3 ),
.delta_cof2 (delta2 ),
.delta_cof1 (delta1 ),
.delta_cof0 (delta0 ),
.data_out_valid (chien_search_out_valid ),
.data_out_start (chien_search_out_start ),
.syndrome_zero_out(syndrome_zero_out_chien ),
.degree_delta (degree_delta ),
.omega (omega ),
.delta (delta ),
.delta_odd (delta_odd )
);
error_correction error_correction
( .clk (clk ),
.n_rst (n_rst ),
.clken (clken ),
.phase1 (phase1 ),
.bypass (bypass ),
.data_in_valid (chien_search_out_valid ),
.data_in_start (chien_search_out_start ),
.syndrome_zero_in (syndrome_zero_out_chien ),
.pipeline_counter (pipeline_counter ),
.degree_delta (degree_delta ),
.omega_in (omega ),
.delta_in (delta ),
.delta_odd_in (delta_odd ),
.data_in (msg_delayed ),
.addr_latch_in (addr_latch ),
.data_out_valid (data_out_valid ),
.data_out_start (data_out_start ),
.corrected_output (corrected_output ),
.correct_fail (frame_err ),
.mpeg_data_valid (mpeg_data_valid ),
.number_corrected (number_corrected )
);
rs_inner_buffer rs_inner_buffer
( .clk (clk ),
.n_rst (n_rst ),
.clken (clken ),
.phase1 (phase1 ),
.data_in_valid (data_in_valid ),
.data_in_start (data_in_start ),
.data_in (symbol ),
.addr_latch (addr_latch ),
.data_out (msg_delayed )
);
//Bert_0,Bert_1,Bert_2
reg [7:0] Bert_0;
reg [7:0] Bert_0_latch;
reg [7:0] Bert_1;
reg [7:0] Bert_2;
reg [25:0] test_counter;
always@(posedge clk or negedge n_rst)
begin
if( n_rst == 1'b0 )
Bert_0 <= 8'h0;
else if( ( Bert_0[7] == 1'b1 && clken == 1'b1 && phase1 == 1'b1 ) &&
( ( Bert_0[2:0] == 3'h0 && test_counter == 26'hfff ) ||
( Bert_0[2:0] == 3'h1 && test_counter == 26'h3fff ) ||
( Bert_0[2:0] == 3'h2 && test_counter == 26'hffff ) ||
( Bert_0[2:0] == 3'h3 && test_counter == 26'h3ffff ) ||
( Bert_0[2:0] == 3'h4 && test_counter == 26'hfffff ) ||
( Bert_0[2:0] == 3'h5 && test_counter == 26'h3fffff ) ||
( Bert_0[2:0] == 3'h6 && test_counter == 26'hffffff ) ||
( Bert_0[2:0] == 3'h7 && test_counter == 26'h3ffffff ) ) )
Bert_0 <= 8'h0;
else if( i2c_addr == 8'ha0 && i2c_wr_en == 1'b1 )
Bert_0 <= i2c_din;
else;
end
always@(posedge clk or negedge n_rst)
begin
if( n_rst == 1'b0 )
Bert_0_latch <= 8'h0;
else if( clken == 1'b1 && phase1 == 1'b1 )
Bert_0_latch <= Bert_0;
else;
end
always@(posedge clk or negedge n_rst)
begin
if( n_rst == 1'b0 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h0 && clken == 1'b1 && test_counter == 26'hfff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h1 && clken == 1'b1 && test_counter == 26'h3fff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h2 && clken == 1'b1 && test_counter == 26'hffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h3 && clken == 1'b1 && test_counter == 26'h3ffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h4 && clken == 1'b1 && test_counter == 26'hfffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h5 && clken == 1'b1 && test_counter == 26'h3fffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h6 && clken == 1'b1 && test_counter == 26'hffffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && Bert_0[2:0] == 3'h7 && clken == 1'b1 && test_counter == 26'h3ffffff && phase1 == 1'b1 )
test_counter <= 26'h0;
else if( Bert_0[7] == 1'b1 && clken == 1'b1 && phase1 == 1'b1 )
test_counter <= test_counter + 1;
else;
end
always@( posedge clk or negedge n_rst )
begin
if( n_rst == 1'b0 )
{ Bert_2 , Bert_1 } <= 16'h0;
else if( Bert_0_latch[7] == 1'b0 && Bert_0[7] == 1'b1 && clken == 1'b1 && phase1 == 1'b1 )
{ Bert_2 , Bert_1 } <= 16'h0;
else if( Bert_0[7] == 1'b1 && clken == 1'b1 && data_out_start == 1'b1 && phase1 == 1'b1 )
{ Bert_2 , Bert_1 } <= { Bert_2 , Bert_1 } + number_corrected;
else;
end
endmodule
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