error_correction.v

rs的译码器

      data_out_start <= 1'b0;
    else;
  end

//The following registers are prepared for baud rate adaption
reg          A_flag;
reg   [7:0]  A_location7 , A_err_value7 , B_location7 , B_err_value7 ;
reg   [7:0]  A_location6 , A_err_value6 , B_location6 , B_err_value6 ;
reg   [7:0]  A_location5 , A_err_value5 , B_location5 , B_err_value5 ;
reg   [7:0]  A_location4 , A_err_value4 , B_location4 , B_err_value4 ;
reg   [7:0]  A_location3 , A_err_value3 , B_location3 , B_err_value3 ;
reg   [7:0]  A_location2 , A_err_value2 , B_location2 , B_err_value2 ;
reg   [7:0]  A_location1 , A_err_value1 , B_location1 , B_err_value1 ;
reg   [7:0]  A_location0 , A_err_value0 , B_location0 , B_err_value0 ;

always@( posedge clk or negedge n_rst )
  begin
    if( n_rst == 1'b0 )
      A_flag <= 1'b0;
    else if ( data_in_start == 1'b1 && clken == 1'b1 )
      A_flag <= ~A_flag;
    else if ( clken == 1'b1 )
      A_flag <=  A_flag;
    else;
  end        

always@( posedge clk or negedge n_rst )
  begin
    if( n_rst == 1'b0 )  
      begin
      A_location7 <= 8'hff ; A_err_value7 <= 8'h0 ; B_location7 <= 8'hff ; B_err_value7 <= 8'h0 ;
      A_location6 <= 8'hff ; A_err_value6 <= 8'h0 ; B_location6 <= 8'hff ; B_err_value6 <= 8'h0 ;
      A_location5 <= 8'hff ; A_err_value5 <= 8'h0 ; B_location5 <= 8'hff ; B_err_value5 <= 8'h0 ;
      A_location4 <= 8'hff ; A_err_value4 <= 8'h0 ; B_location4 <= 8'hff ; B_err_value4 <= 8'h0 ;
      A_location3 <= 8'hff ; A_err_value3 <= 8'h0 ; B_location3 <= 8'hff ; B_err_value3 <= 8'h0 ;
      A_location2 <= 8'hff ; A_err_value2 <= 8'h0 ; B_location2 <= 8'hff ; B_err_value2 <= 8'h0 ;
      A_location1 <= 8'hff ; A_err_value1 <= 8'h0 ; B_location1 <= 8'hff ; B_err_value1 <= 8'h0 ;
      A_location0 <= 8'hff ; A_err_value0 <= 8'h0 ; B_location0 <= 8'hff ; B_err_value0 <= 8'h0 ;
      end
    else if( clken == 1'b1 && data_out_start == 1'b1 && phase1 == 1'b1 && A_flag == 1'b1 )
      begin
      A_location7 <= A_location7 ; A_err_value7 <= A_err_value7 ; B_location7 <= 8'hff ; B_err_value7 <= 8'h0 ;
      A_location6 <= A_location6 ; A_err_value6 <= A_err_value6 ; B_location6 <= 8'hff ; B_err_value6 <= 8'h0 ;
      A_location5 <= A_location5 ; A_err_value5 <= A_err_value5 ; B_location5 <= 8'hff ; B_err_value5 <= 8'h0 ;
      A_location4 <= A_location4 ; A_err_value4 <= A_err_value4 ; B_location4 <= 8'hff ; B_err_value4 <= 8'h0 ;
      A_location3 <= A_location3 ; A_err_value3 <= A_err_value3 ; B_location3 <= 8'hff ; B_err_value3 <= 8'h0 ;
      A_location2 <= A_location2 ; A_err_value2 <= A_err_value2 ; B_location2 <= 8'hff ; B_err_value2 <= 8'h0 ;
      A_location1 <= A_location1 ; A_err_value1 <= A_err_value1 ; B_location1 <= 8'hff ; B_err_value1 <= 8'h0 ;
      A_location0 <= A_location0 ; A_err_value0 <= A_err_value0 ; B_location0 <= 8'hff ; B_err_value0 <= 8'h0 ;
      end
    else if( clken == 1'b1 && data_out_start == 1'b1 && phase1 == 1'b1 && A_flag == 1'b0 )
      begin
      A_location7 <= 8'hff ; A_err_value7 <= 8'h0 ; B_location7 <= B_location7 ; B_err_value7 <= B_err_value7 ;
      A_location6 <= 8'hff ; A_err_value6 <= 8'h0 ; B_location6 <= B_location6 ; B_err_value6 <= B_err_value6 ;
      A_location5 <= 8'hff ; A_err_value5 <= 8'h0 ; B_location5 <= B_location5 ; B_err_value5 <= B_err_value5 ;
      A_location4 <= 8'hff ; A_err_value4 <= 8'h0 ; B_location4 <= B_location4 ; B_err_value4 <= B_err_value4 ;
      A_location3 <= 8'hff ; A_err_value3 <= 8'h0 ; B_location3 <= B_location3 ; B_err_value3 <= B_err_value3 ;
      A_location2 <= 8'hff ; A_err_value2 <= 8'h0 ; B_location2 <= B_location2 ; B_err_value2 <= B_err_value2 ;
      A_location1 <= 8'hff ; A_err_value1 <= 8'h0 ; B_location1 <= B_location1 ; B_err_value1 <= B_err_value1 ;
      A_location0 <= 8'hff ; A_err_value0 <= 8'h0 ; B_location0 <= B_location0 ; B_err_value0 <= B_err_value0 ;
      end
    else if( ( symbol_counter_latch != 8'h0 || symbol_counter != 8'h0 ) 
            && A_flag == 1'b1 && clken == 1'b1 && error_value != 8'h0 )
      begin
      A_location7 <= A_location6          ; A_err_value7 <= A_err_value6 ; B_location7 <= B_location7 ; B_err_value7 <= B_err_value7 ;
      A_location6 <= A_location5          ; A_err_value6 <= A_err_value5 ; B_location6 <= B_location6 ; B_err_value6 <= B_err_value6 ;
      A_location5 <= A_location4          ; A_err_value5 <= A_err_value4 ; B_location5 <= B_location5 ; B_err_value5 <= B_err_value5 ;
      A_location4 <= A_location3          ; A_err_value4 <= A_err_value3 ; B_location4 <= B_location4 ; B_err_value4 <= B_err_value4 ;
      A_location3 <= A_location2          ; A_err_value3 <= A_err_value2 ; B_location3 <= B_location3 ; B_err_value3 <= B_err_value3 ;
      A_location2 <= A_location1          ; A_err_value2 <= A_err_value1 ; B_location2 <= B_location2 ; B_err_value2 <= B_err_value2 ;
      A_location1 <= A_location0          ; A_err_value1 <= A_err_value0 ; B_location1 <= B_location1 ; B_err_value1 <= B_err_value1 ;
      A_location0 <= symbol_counter_latch ; A_err_value0 <= error_value  ; B_location0 <= B_location0 ; B_err_value0 <= B_err_value0 ;
      end
    else if( ( symbol_counter_latch != 8'h0 || symbol_counter != 8'h0 ) 
            && A_flag == 1'b0 && clken == 1'b1 && error_value != 8'h0 )
      begin
      A_location7 <= A_location7 ; A_err_value7 <= A_err_value7 ; B_location7 <= B_location6          ; B_err_value7 <= B_err_value6 ;
      A_location6 <= A_location6 ; A_err_value6 <= A_err_value6 ; B_location6 <= B_location5          ; B_err_value6 <= B_err_value5 ;
      A_location5 <= A_location5 ; A_err_value5 <= A_err_value5 ; B_location5 <= B_location4          ; B_err_value5 <= B_err_value4 ;
      A_location4 <= A_location4 ; A_err_value4 <= A_err_value4 ; B_location4 <= B_location3          ; B_err_value4 <= B_err_value3 ;
      A_location3 <= A_location3 ; A_err_value3 <= A_err_value3 ; B_location3 <= B_location2          ; B_err_value3 <= B_err_value2 ;
      A_location2 <= A_location2 ; A_err_value2 <= A_err_value2 ; B_location2 <= B_location1          ; B_err_value2 <= B_err_value1 ;
      A_location1 <= A_location1 ; A_err_value1 <= A_err_value1 ; B_location1 <= B_location0          ; B_err_value1 <= B_err_value0 ;
      A_location0 <= A_location0 ; A_err_value0 <= A_err_value0 ; B_location0 <= symbol_counter_latch ; B_err_value0 <= error_value  ;
      end
    else;  
  end    

reg         output_flag;
always@( posedge clk or negedge n_rst )
  begin
    if( n_rst == 1'b0 )
      output_flag <= 1'b0;
    else if( pipeline_counter == 8'hca && clken == 1'b1 && phase1 == 1'b1 )
      output_flag <= A_flag;
    else;
  end

reg   [7:0]   msg_delayed;
always@( posedge clk or negedge n_rst )
  begin
    if( n_rst == 1'b0 )
      msg_delayed <= 8'h0;
    else if ( clken == 1'b1 && phase_counter == 2'h0 )
      msg_delayed <= data_in;
    else;
  end  

reg   [8:0]   addr_out;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      addr_out <= 9'h0;
    else if ( clken == 1'b1 && phase1 == 1'b1 )
      addr_out <= addr_latch_in;
    else;
  end

reg    [7:0]  corrected_output;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      corrected_output <= 8'h0;
    else if ( clken == 1'b1 && bypass == 1'b1 && phase1 == 1'b1 )
      corrected_output <= msg_delayed;
    else if ( clken == 1'b1 && phase1 == 1'b1 && syndrome_zero_latch == 1'b1 )
      corrected_output <= msg_delayed;
      
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location7 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value7 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location6 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value6 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location5 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value5 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location4 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value4 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location3 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value3 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location2 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value2 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location1 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value1 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && pipeline_counter == 8'hcb && A_location0 == 8'h0 )
      corrected_output <= msg_delayed ^ A_err_value0 ;
    
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location7 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value7 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location6 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value6 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location5 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value5 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location4 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value4 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location3 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value3 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location2 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value2 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location1 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value1 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && pipeline_counter == 8'hcb && B_location0 == 8'h0 )
      corrected_output <= msg_delayed ^ B_err_value0 ;
    
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location7 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value7 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location6 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value6 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location5 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value5 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location4 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value4 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location3 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value3 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location2 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value2 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location1 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value1 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b1 && A_location0 == addr_out )
      corrected_output <= msg_delayed ^ A_err_value0 ;
    
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location7 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value7 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location6 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value6 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location5 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value5 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location4 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value4 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location3 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value3 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location2 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value2 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location1 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value1 ;
    else if ( clken == 1'b1 && phase1 == 1'b1 && output_flag == 1'b0 && B_location0 == addr_out )
      corrected_output <= msg_delayed ^ B_err_value0 ;
    
    else if ( clken == 1'b1 && phase1 == 1'b1 )
      corrected_output <= msg_delayed;
    else;
  end  

reg           mpeg_data_valid;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      mpeg_data_valid <= 1'b0; 
    else if ( clken == 1'b1 && phase1 == 1'b1 && data_out_valid == 1'b1 && pipeline_counter >= 8'hbb && pipeline_counter <= 8'hca )
      mpeg_data_valid <= 1'b0;
    else if (  clken == 1'b1 && phase1 == 1'b1 )
      mpeg_data_valid <= 1'b1;
    else;
  end

endmodule