error_correction.v

rs的译码器

                                    
//                                                                                          
//Design       : Reed-Solomon decoder RS(204,188) in QAM                                    
//                                                                                          
//File Name    : error_correction.v                                                         
//                                                                                          
//Perpose      : compute the error value at each locator                                    
//                                                                                          
             
                                                                                            
//synopsys translate_off                                                                    
`include  "timescale.v"                                                                     
//synopsys translate_on

module error_correction ( clk                 ,
                          n_rst               ,
                          clken               ,
                          phase1              ,
                          bypass              ,
                          data_in_valid       ,
                          data_in_start       ,
                          syndrome_zero_in    ,
                          pipeline_counter    ,
                          degree_delta        ,
                          omega_in            ,
                          delta_in            ,
                          delta_odd_in        ,
                          data_in             ,
                          addr_latch_in       ,
                          data_out_valid      ,
                          data_out_start      ,
                          corrected_output    ,
                          correct_fail        ,
                          mpeg_data_valid     ,
                          number_corrected
                         );

//Port declaration 
input                     clk                 ;
input                     n_rst               ;
input                     clken               ;
input                     phase1              ;
input                     bypass              ;
input                     data_in_valid       ;
input                     data_in_start       ;
input                     syndrome_zero_in    ;
input  [7:0]              pipeline_counter    ;                 
input  [4:0]              degree_delta        ;
input  [7:0]              omega_in            ;
input  [7:0]              delta_in            ;
input  [7:0]              delta_odd_in        ;
input  [7:0]              data_in             ;
input  [8:0]              addr_latch_in       ;
                                               
output                    data_out_valid      ;
output                    data_out_start      ;
output [7:0]              corrected_output    ;
output                    correct_fail        ;
output                    mpeg_data_valid     ;
output [4:0]              number_corrected    ;

//////////////////////////////////////////////////////////////////
//The forney error correction logic
wire   [7:0]              inv_delta_odd       ;
wire   [7:0]              com_delta           ;
wire   [7:0]              forney              ;
wire   [7:0]              error_value         ;

reg    [7:0]              omega_delay         ;
reg    [7:0]              inv_delta_odd_delay ;
reg    [7:0]              com_delta_delay     ;

inverter8     Inv      ( .a (delta_odd_in  ) ,
                         .b (inv_delta_odd )
                        );

assign        com_delta  = ( delta_in == 8'h0 ) ?  8'hff : 8'h0 ;

always@(posedge clk or negedge n_rst)
  begin
    if( n_rst == 1'b0 )
      begin
        omega_delay               <= 8'h0;
        inv_delta_odd_delay       <= 8'h0;
        com_delta_delay           <= 8'h0;
      end
    else if ( clken == 1'b1 )
      begin
        omega_delay               <= omega_in;
        inv_delta_odd_delay       <= inv_delta_odd;
        com_delta_delay           <= com_delta;
      end
    else;
  end

parallel_PB_mul_8  M_forey ( .a   (omega_delay         ) ,
                             .b   (inv_delta_odd_delay ) ,
                             .sel (1'b0                ) ,
                             .c   (forney              )  
                            );

assign        error_value  =  com_delta_delay & forney ;

//The above logic perform the error value computation////////
///////////////////////////////////////////////////////////// 


/////////////////////////////////////////////////////////////
//Infer the auxiliary logic
reg    [1:0]             phase_counter    ;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      phase_counter <= 2'h0;
    else if ( phase1 == 1'b1 && clk == 1'b1 )
      phase_counter <= 2'h0;
    else if ( clken == 1'b1 )
      phase_counter <= phase_counter + 1;
    else;
  end

reg   [7:0]  symbol_counter;
always@(posedge clk or negedge n_rst)
  begin
    if ( n_rst == 1'b0 )
      symbol_counter <= 8'h0;
    else if ( data_in_valid == 1'b0 && clken == 1'b1 )
      symbol_counter <= 8'h0;
    else if ( data_in_start == 1'b0 && symbol_counter == 8'h0 && clken == 1'b1 )
      symbol_counter <= 8'h0;
    else if ( symbol_counter == 8'hcb && clken == 1'b1 )
      symbol_counter <= 8'h0;
    else if ( clken == 1'b1 )
      symbol_counter <= symbol_counter + 1;
    else;
  end

reg   [7:0]  symbol_counter_latch;
always@( posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      symbol_counter_latch <= 8'h0;
    else if ( clken == 1'b1 )
      symbol_counter_latch <= symbol_counter;
    else;
  end


reg          syndrome_zero_latch;
always@(posedge clk or negedge n_rst)
  begin
    if ( n_rst == 1'b0 )
      syndrome_zero_latch <= 1'b1;
    else if ( data_in_start == 1'b1 && clken == 1'b1 )
      syndrome_zero_latch <= syndrome_zero_in;
    else if ( clken == 1'b1 )
      syndrome_zero_latch <= syndrome_zero_latch;
    else;
  end

reg  [4:0]   number_corrected;
always@(posedge clk or negedge n_rst)
  begin
    if ( n_rst == 1'b0 )
      number_corrected <= 5'h0;
    else if ( data_in_start == 1'b1 && syndrome_zero_in == 1'b1 && clken == 1'b1 )
      number_corrected <= 5'h0;
    else if ( data_in_start == 1'b1 && syndrome_zero_in == 1'b0 && delta_in == 8'h0 && clken == 1'b1 )
      number_corrected <= 5'h1;
    else if ( data_in_start == 1'b1 && syndrome_zero_in == 1'b0 && delta_in != 8'h0 && clken == 1'b1 )
      number_corrected <= 5'h0;
    else if ( symbol_counter != 8'h0 && syndrome_zero_latch == 1'b1 && clken == 1'b1 ) 
      number_corrected <= 5'h0;
    else if ( symbol_counter != 8'h0 && delta_in == 8'h0 && clken == 1'b1 )
      number_corrected <= number_corrected + 1 ; 
    else if ( clken == 1'b1 )
      number_corrected <= number_corrected ;
    else;
  end

reg          correct_fail;
always@(posedge clk or negedge n_rst)
  begin
    if ( n_rst == 1'b0 )
      correct_fail <= 1'b0;
    else if ( bypass == 1'b1 && clken == 1'b1 && phase1 ==1'b1 )
      correct_fail <= 1'b0;
    else if ( pipeline_counter == 8'hcb && syndrome_zero_latch == 1'b1 && clken == 1'b1 && phase1 ==1'b1 )
      correct_fail <= 1'b0;
    else if ( pipeline_counter == 8'hcb && number_corrected != degree_delta && clken == 1'b1 && phase1 ==1'b1 )
      correct_fail <= 1'b1;
    else if ( pipeline_counter == 8'hcb && number_corrected == degree_delta && clken == 1'b1 && phase1 ==1'b1 )
      correct_fail <= 1'b0;
    else if ( clken == 1'b1 && phase1 ==1'b1 )
      correct_fail <= correct_fail;
    else;
  end

reg          data_out_valid;
always@(posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      data_out_valid <= 1'b0;
    else if ( clken == 1'b1 && phase1 ==1'b1 )
      data_out_valid <= data_in_valid;
    else;
  end

reg          data_out_start;
always@(posedge clk or negedge n_rst )
  begin
    if ( n_rst == 1'b0 )
      data_out_start <= 1'b0;
    else if ( pipeline_counter == 8'hcb && clken == 1'b1 && phase1 ==1'b1 )  
      data_out_start <= 1'b1;
    else if ( clken == 1'b1 && phase1 ==1'b1 )