📄 mea.v
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//
//Design : Reed-Solomon decoder RS(204,188) in QAM
//
//File Name : MEA.v
//
//Perpose : Modified Euclidian Algorithem used to obtain the error locator polynomial
// and the error value polynomial
//
//Limitations : None
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module MEA ( clk , n_rst , syndrome_in ,
data_out_valid , data_out_start ,
delta16 , omega16 , data_in_valid ,
delta15 , omega15 , syndrome15 ,
delta14 , omega14 , syndrome14 ,
delta13 , omega13 , syndrome13 ,
delta12 , omega12 , syndrome12 ,
delta11 , omega11 , syndrome11 ,
delta10 , omega10 , syndrome10 ,
delta9 , omega9 , syndrome9 ,
delta8 , omega8 , syndrome8 ,
delta7 , omega7 , syndrome7 ,
delta6 , omega6 , syndrome6 ,
delta5 , omega5 , syndrome5 ,
delta4 , omega4 , syndrome4 ,
delta3 , omega3 , syndrome3 ,
delta2 , omega2 , syndrome2 ,
delta1 , omega1 , syndrome1 ,
delta0 , omega0 , syndrome0 ,
syndrome_zero , clken , phase1,
pipeline_counter
);
input clk ;
input clken ;
input phase1 ;
input n_rst ;
input syndrome_in ;
input data_in_valid ;
input [7:0] syndrome15 ;
input [7:0] syndrome14 ;
input [7:0] syndrome13 ;
input [7:0] syndrome12 ;
input [7:0] syndrome11 ;
input [7:0] syndrome10 ;
input [7:0] syndrome9 ;
input [7:0] syndrome8 ;
input [7:0] syndrome7 ;
input [7:0] syndrome6 ;
input [7:0] syndrome5 ;
input [7:0] syndrome4 ;
input [7:0] syndrome3 ;
input [7:0] syndrome2 ;
input [7:0] syndrome1 ;
input [7:0] syndrome0 ;
output data_out_start, data_out_valid ;
output [7:0] delta16 , omega16 ;
output [7:0] delta15 , omega15 ;
output [7:0] delta14 , omega14 ;
output [7:0] delta13 , omega13 ;
output [7:0] delta12 , omega12 ;
output [7:0] delta11 , omega11 ;
output [7:0] delta10 , omega10 ;
output [7:0] delta9 , omega9 ;
output [7:0] delta8 , omega8 ;
output [7:0] delta7 , omega7 ;
output [7:0] delta6 , omega6 ;
output [7:0] delta5 , omega5 ;
output [7:0] delta4 , omega4 ;
output [7:0] delta3 , omega3 ;
output [7:0] delta2 , omega2 ;
output [7:0] delta1 , omega1 ;
output [7:0] delta0 , omega0 ;
output syndrome_zero ;
output [7:0] pipeline_counter;
reg [7:0] R16 , Q16 , L16 , U16 ;
reg [7:0] R15 , Q15 , L15 , U15 ;
reg [7:0] R14 , Q14 , L14 , U14 ;
reg [7:0] R13 , Q13 , L13 , U13 ;
reg [7:0] R12 , Q12 , L12 , U12 ;
reg [7:0] R11 , Q11 , L11 , U11 ;
reg [7:0] R10 , Q10 , L10 , U10 ;
reg [7:0] R9 , Q9 , L9 , U9 ;
reg [7:0] R8 , Q8 , L8 , U8 ;
reg [7:0] R7 , Q7 , L7 , U7 ;
reg [7:0] R6 , Q6 , L6 , U6 ;
reg [7:0] R5 , Q5 , L5 , U5 ;
reg [7:0] R4 , Q4 , L4 , U4 ;
reg [7:0] R3 , Q3 , L3 , U3 ;
reg [7:0] R2 , Q2 , L2 , U2 ;
reg [7:0] R1 , Q1 , L1 , U1 ;
reg [7:0] R0 , Q0 , L0 , U0 ;
reg start_calc, start_calc_latch ;
reg [7:0] pipeline_counter;
reg [2:0] current_state, next_state;
reg [4:0] shift_counter;
reg [4:0] reload_counter;
reg data_out_valid ;
reg syndrome_zero;
wire [4:0] li;
wire [7:0] ai;
wire [7:0] bi;
wire swap;
wire stop;
wire [7:0] Q_cof16 ;
wire [7:0] Q_cof15 ;
wire [7:0] Q_cof14 ;
wire [7:0] Q_cof13 ;
wire [7:0] Q_cof12 ;
wire [7:0] Q_cof11 ;
wire [7:0] Q_cof10 ;
wire [7:0] Q_cof9 ;
wire [7:0] Q_cof8 ;
wire [7:0] Q_cof7 ;
wire [7:0] Q_cof6 ;
wire [7:0] Q_cof5 ;
wire [7:0] Q_cof4 ;
wire [7:0] Q_cof3 ;
wire [7:0] Q_cof2 ;
wire [7:0] Q_cof1 ;
wire [7:0] Q_cof0 ;
wire [7:0] result_RQ;
wire [7:0] result_LU;
wire [7:0] CU_R;
wire [7:0] CU_Q;
wire [7:0] CU_L;
wire [7:0] CU_U;
assign Q_cof16 = (current_state == 3'h0) ? 8'h0 : Q16 ;
assign Q_cof15 = (current_state == 3'h0) ? syndrome15 : Q15 ;
assign Q_cof14 = (current_state == 3'h0) ? syndrome14 : Q14 ;
assign Q_cof13 = (current_state == 3'h0) ? syndrome13 : Q13 ;
assign Q_cof12 = (current_state == 3'h0) ? syndrome12 : Q12 ;
assign Q_cof11 = (current_state == 3'h0) ? syndrome11 : Q11 ;
assign Q_cof10 = (current_state == 3'h0) ? syndrome10 : Q10 ;
assign Q_cof9 = (current_state == 3'h0) ? syndrome9 : Q9 ;
assign Q_cof8 = (current_state == 3'h0) ? syndrome8 : Q8 ;
assign Q_cof7 = (current_state == 3'h0) ? syndrome7 : Q7 ;
assign Q_cof6 = (current_state == 3'h0) ? syndrome6 : Q6 ;
assign Q_cof5 = (current_state == 3'h0) ? syndrome5 : Q5 ;
assign Q_cof4 = (current_state == 3'h0) ? syndrome4 : Q4 ;
assign Q_cof3 = (current_state == 3'h0) ? syndrome3 : Q3 ;
assign Q_cof2 = (current_state == 3'h0) ? syndrome2 : Q2 ;
assign Q_cof1 = (current_state == 3'h0) ? syndrome1 : Q1 ;
assign Q_cof0 = (current_state == 3'h0) ? syndrome0 : Q0 ;
degree_calc DC ( .clk(clk) , .n_rst(n_rst ) , .start_calc(start_calc) , .clken(clken) ,
.R16(R16) , .Q16 (Q_cof16) , .L16 (L16 ) ,
.R15(R15) , .Q15 (Q_cof15) , .L15 (L15 ) ,
.R14(R14) , .Q14 (Q_cof14) , .L14 (L14 ) ,
.R13(R13) , .Q13 (Q_cof13) , .L13 (L13 ) ,
.R12(R12) , .Q12 (Q_cof12) , .L12 (L12 ) ,
.R11(R11) , .Q11 (Q_cof11) , .L11 (L11 ) ,
.R10(R10) , .Q10 (Q_cof10) , .L10 (L10 ) ,
.R9 (R9 ) , .Q9 (Q_cof9 ) , .L9 (L9 ) ,
.R8 (R8 ) , .Q8 (Q_cof8 ) , .L8 (L8 ) ,
.R7 (R7 ) , .Q7 (Q_cof7 ) , .L7 (L7 ) ,
.R6 (R6 ) , .Q6 (Q_cof6 ) , .L6 (L6 ) ,
.R5 (R5 ) , .Q5 (Q_cof5 ) , .L5 (L5 ) ,
.R4 (R4 ) , .Q4 (Q_cof4 ) , .L4 (L4 ) ,
.R3 (R3 ) , .Q3 (Q_cof3 ) , .L3 (L3 ) ,
.R2 (R2 ) , .Q2 (Q_cof2 ) , .L2 (L2 ) ,
.R1 (R1 ) , .Q1 (Q_cof1 ) , .L1 (L1 ) ,
.R0 (R0 ) , .Q0 (Q_cof0 ) , .L0 (L0 ) ,
.li (li ) , .swap (swap ) , .stop(stop) , .ai(ai) , .bi(bi) , .phase1(phase1)
);
assign CU_R = ( li >= 16 - reload_counter && current_state == 3'h5 ) ? 8'h0 : R16;
assign CU_Q = ( li >= 16 - reload_counter && current_state == 3'h4 ) ? 8'h0 : Q16;
assign CU_L = ( li >= 16 - reload_counter && current_state == 3'h5 ) ? 8'h0 : L16;
assign CU_U = ( li >= 16 - reload_counter && current_state == 3'h4 ) ? 8'h0 : U16;
CU CU_RQ ( .ai(ai) , .bi(bi) , .RL(CU_R) , .QU(CU_Q) , .result(result_RQ) );
CU CU_LU ( .ai(ai) , .bi(bi) , .RL(CU_L) , .QU(CU_U) , .result(result_LU) );
//Infer the register of pipeline counter
always@(posedge clk or negedge n_rst)
begin
if ( n_rst == 1'b0 )
pipeline_counter <= 8'h0;
else if ( data_in_valid == 1'b0 && clken == 1'b1 && phase1 == 1'b1 )
pipeline_counter <= 8'h0;
else if ( data_in_valid == 1'b1 && syndrome_in == 1'b0 && pipeline_counter == 8'h0 && clken == 1'b1 && phase1 == 1'b1 )
pipeline_counter <= 8'h0;
else if ( data_in_valid == 1'b1 && pipeline_counter == 8'hcb && clken == 1'b1 && phase1 == 1'b1 )
pipeline_counter <= 8'h0;
else if ( clken == 1'b1 && phase1 == 1'b1 )
pipeline_counter <= pipeline_counter + 1;
else;
end
//infer the register of start_calc_latch
always@(posedge clk or negedge n_rst)
begin
if ( n_rst == 1'b0 )
start_calc_latch <= 1'b0;
else if ( clken == 1'b1 && phase1 == 1'b1 )
start_calc_latch <= start_calc;
else;
end
//infer the register of shift_counter which control the shift taps before reload
always@(posedge clk or negedge n_rst )
begin
if ( n_rst == 1'b0 )
shift_counter <= 5'h0;
else if ( shift_counter != 5'h0 && clken == 1'b1 && phase1 == 1'b1 )
shift_counter <= shift_counter - 1;
else if ( start_calc_latch == 1'b1 && li >= 5'h1 && clken == 1'b1 && phase1 == 1'b1 )
shift_counter <= li - 1 ;
else if ( clken == 1'b1 && phase1 == 1'b1 )
shift_counter <= 5'h0;
else;
end
//infer the register of reload_counter which control the shift taps of reload
always@(posedge clk or negedge n_rst )
begin
if ( n_rst == 1'b0 )
reload_counter <= 5'h0;
else if ( (current_state == 3'h4 || current_state == 3'h5) && reload_counter == 5'h11 && clken == 1'b1 && phase1 == 1'b1 )
reload_counter <= 5'h0;
else if ( (current_state == 3'h4 || current_state == 3'h5) && reload_counter == 5'h11 && clken == 1'b1 )
reload_counter <= reload_counter;
else if ( (current_state == 3'h4 || current_state == 3'h5) && clken == 1'b1 )
reload_counter <= reload_counter + 1;
else;
end
//The main state machine
parameter idle = 3'h0,
ready = 3'h1,
shift_non_swap = 3'h2,
shift_with_swap = 3'h3,
non_swap_reload = 3'h4,
swap_reload = 3'h5;
always@( posedge clk or negedge n_rst )
begin
if ( n_rst == 1'b0 )
current_state <= 3'h0;
else if ( clken == 1'b1 && phase1 == 1'b1 )
current_state <= next_state;
else;
end
always@( current_state or li or swap or stop or ai or bi or syndrome_in or shift_counter or reload_counter)
begin
case(current_state)
idle :
begin
start_calc = syndrome_in;
if ( syndrome_in == 1'b1 )
next_state = ready;
else
next_state = idle;
end
ready :
begin
start_calc = 1'b0;
if ( stop == 1'b1 )
next_state = idle;
else if ( li == 5'h0 )
next_state = non_swap_reload;
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