用verilog 实现一个16位超前进位加法器.txt

16位快速加法器verilong实现

16位超前进位加法器
module cla16 (a,b,s);  //top module 含有四个4 位超前进位加法器子模块
input [15:0] a, b;
output [15:0] s;

wire pp4,pp3,pp2,pp1;
wire gg4,gg3,gg2,gg1;
wire [14:0] Cp;

wire [15:0] p,g;


claslice i1 (p[3],p[2],p[1],p[0],g[3],g[2],g[1],g[0],1'b0,Cp[2],Cp[1],Cp[0],pp1,gg1);
claslice i2 (p[7],p[6],p[5],p[4],g[7],g[6],g[5],g[4],Cp[3],Cp[6],Cp[5],Cp[4],pp2,gg2);
claslice i3 (p[11],p[10],p[9],p[8],g[11],g[10],g[9],g[8],Cp[7],Cp[10],Cp[9],Cp[8],pp3,gg3);
claslice i4 (p[15],p[14],p[13],p[12],g[15],g[14],g[13],g[12],Cp[11],Cp[14],Cp[13],Cp[12],pp4,gg4);
claslice i5 (pp4,pp3,pp2,pp1,gg4,gg3,gg2,gg1,1'b0,Cp[11],Cp[7],Cp[3],pp5,gg5);

pg i0(a[15:0],b[15:0],p[15:0],g[15:0]);

assign s[0]=p[0]^1'b0;
assign s[1]=p[1]^Cp[0];
assign s[2]=p[2]^Cp[1];
assign s[3]=p[3]^Cp[2];
assign s[4]=p[4]^Cp[3];
assign s[5]=p[5]^Cp[4];
assign s[6]=p[6]^Cp[5];
assign s[7]=p[7]^Cp[6];
assign s[8]=p[8]^Cp[7];
assign s[9]=p[9]^Cp[8];
assign s[10]=p[10]^Cp[9];
assign s[11]=p[11]^Cp[10];
assign s[12]=p[12]^Cp[11];
assign s[13]=p[13]^Cp[12];
assign s[14]=p[14]^Cp[13];
assign s[15]=p[15]^Cp[14];

endmodule

module claslice(p[3],p[2],p[1],p[0],g[3],g[2],g[1],g[0],Co,Cp[2],Cp[1],Cp[0],pp,gg);  //4位超前进位加法器模块

input [3:0] p, g;
input Co;
output [2:0] Cp;
output pp,gg;
assign Cp[0]=g[0]|p[0]&Co;
assign Cp[1]=g[1]|p[1]&Cp[0];
assign Cp[2]=g[2]|p[2]&Cp[1];
assign pp=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]|(p[3]&(g[2]|p[2]&(g[1]|p[1]&g[0])));
endmodule

module pg(a,b,p,g);  //进位产生信号、进位传递信号 产生模块
input [15:0] a, b;
output [15:0] p,g;
assign p=a^b;
assign g=a&b;
endmodule



采用kogge-stone tree 的32位超前进位加法器
经modlesim验证正确,并可以用dc综合!
module cla32 (a,b,cin,sum,co);
input [31:0] a,b;
input cin;
output [31:0] sum;
output co;
reg [31:0] G1,P1,G2,P2,G3,P3,G4,P4,G5,P5;
reg [31:0] cout;
wire[31:0] sum,G0,P0;
assign P0=a^b;
assign G0=a&b;
assign sum=P0^{cout[31:0],cin};
assign co=cout[31];
always @(P0 or G0 or P1 or G1 or P2 or G2 or P3 or G3 or P4 or G4 or P5 or G5 )
begin 
  P1[31:1]=P0[31:1]&P0[30:0];
  G1[31:1]=G0[31:1]|P0[31:1]&G0[30:0];
  G1[0]=G0[0];
  P1[0]=P0[0];
  P2[31:2]=P1[31:2]&P1[29:0];
  G2[31:2]=G1[31:2]|P1[31:2]&G1[29:0]; 
  G2[1:0]=G1[1:0];
  P2[1:0]=P1[1:0];
  P3[31:4]=P2[31:4]&P2[27:0];
  G3[31:4]=G2[31:4]|P2[31:4]&G2[27:0]; 
  G3[3:0]=G2[3:0];
  P3[3:0]=P2[3:0];
  P4[31:8]=P3[31:8]&P3[23:0];
  G4[31:8]=G3[31:8]|P3[31:8]&G3[23:0]; 
  G4[7:0]=G3[7:0];
  P4[7:0]=P3[7:0];
  P5[31:16]=P4[31:16]&P4[15:0];
  G5[31:16]=G4[31:16]|P4[31:16]&G4[15:0];
  G5[15:0]=G4[15:0];
  P5[15:0]=P4[15:0];
  cout=G5|P5&cin;  
end
endmodule




32位测试

Verilog Designer's Library的代码--加法器
// MODULE:		adder
//
// FILE NAME:	add_rtl.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Register Transfer Level
//
// DESCRIPTION:	This module defines an adder with
// synchronous add enable and reset inputs. When the adder
// is synchronously reset, the outputs go to zero and the
// valid signal is asserted on the next clock cycle. When
// the add enable input is asserted and the valid output is
// asserted during the same clock cycle, the adder begins
// adding. When the valid output signal is again asserted
// on a subsequent clock cycle, the new output is correct.
// Note that the inputs must be held steady from the cycle
// during which the add enable input is asserted until the
// cycle during which the valid output signal is asserted.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.

// TOP MODULE
module Adder(
		clk,
		a,
		b,
		reset_n,
		add_en,
		out,
		cout,
		valid);

// INPUTS
input			clk;		// Clock
input [31:0]	a;			// 32-bit A input
input [31:0]	b;			// 32-bit B input
input			reset_n;	// Active low, synchronous reset
input			add_en;		// Synchronous add enable control

// OUTPUTS
output [31:0]	out;		// 32-bit output
output 			cout;		// Carry output
output 			valid;		// Is the output valid yet?

// INOUTS

// SIGNAL DECLARATIONS
wire			clk;
wire [31:0]		a;
wire [31:0]		b;
wire			reset_n;
wire			add_en;
wire [31:0]		out;
wire 			cout;
wire 			valid;
wire [7:0]		cout4;		// Carry output of 4-bit adder
reg  [2:0]		valid_cnt;	// Counter to determine when the
							// output is valid

// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL cout = cout4[7];
assign #`DEL valid = ~|valid_cnt;

// MAIN CODE

// Instantiate eight 4-bit adders
Adder_4bit Add0(
		.clk(clk),
		.a(a[3:0]),
		.b(b[3:0]),
		.cin(1'b0),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[3:0]),
		.cout(cout4[0]));

Adder_4bit Add1(
		.clk(clk),
		.a(a[7:4]),
		.b(b[7:4]),
		.cin(cout4[0]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[7:4]),
		.cout(cout4[1]));

Adder_4bit Add2(
		.clk(clk),
		.a(a[11:8]),
		.b(b[11:8]),
		.cin(cout4[1]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[11:8]),
		.cout(cout4[2]));

Adder_4bit Add3(
		.clk(clk),
		.a(a[15:12]),
		.b(b[15:12]),
		.cin(cout4[2]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[15:12]),
		.cout(cout4[3]));

Adder_4bit Add4(
		.clk(clk),
		.a(a[19:16]),
		.b(b[19:16]),
		.cin(cout4[3]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[19:16]),
		.cout(cout4[4]));

Adder_4bit Add5(
		.clk(clk),
		.a(a[23:20]),
		.b(b[23:20]),
		.cin(cout4[4]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[23:20]),
		.cout(cout4[5]));

Adder_4bit Add6(
		.clk(clk),
		.a(a[27:24]),
		.b(b[27:24]),
		.cin(cout4[5]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[27:24]),
		.cout(cout4[6]));

Adder_4bit Add7(
		.clk(clk),
		.a(a[31:28]),
		.b(b[31:28]),
		.cin(cout4[6]),
		.reset_n(reset_n),
		.add_en(add_en),
		.out(out[31:28]),
		.cout(cout4[7]));

// Look at the rising edge of the clock
always @(posedge clk) begin
	if (~reset_n) begin
		// Initialize the valid counter
		valid_cnt <= #`DEL 3'h0;
	end
	else if (((valid_cnt == 3'h0) && (add_en == 1'b1)) ||
		  (valid_cnt != 3'h0)) begin
		// Increment the valid counter
		// if valid and add_en are asserted
		// or if valid is not asserted
		valid_cnt <= #`DEL valid_cnt + 1;
	end
end
endmodule		// Adder

// SUB MODULE
module	Adder_4bit(
		clk,
		a,
		b,
		reset_n,
		add_en,
		cin,
		out,
		cout);

// INPUTS
input			clk;		// Clock
input [3:0]		a;			// 4-bit A input
input [3:0]		b;			// 4-bit B input
input			cin;		// Carry in
input			reset_n;	// Active low, synchronous reset
input			add_en;		// Synchronous add enable control

// OUTPUTS
output [3:0]	out;		// 4-bit output
output 			cout;		// Carry output

// INOUTS

// SIGNAL DECLARATIONS
wire			clk;
wire [3:0]		a;
wire [3:0]		b;
wire			cin;
wire			reset_n;
wire			add_en;
reg  [3:0]		out;
reg 			cout;

// ASSIGN STATEMENTS

// PARAMETERS

// MAIN CODE

// Look at the rising edge of the clock
always @(posedge clk) begin
	if (~reset_n) begin
		{cout,out} <= #`DEL 33'h00000000;
	end
	else if (add_en) begin
		{cout,out} <= #`DEL a+b+cin;
	end
end
endmodule			// Adder_4bit