shuzibiao.map.qmsg

数字钟的verilog代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 21 19:53:45 2008 " "Info: Processing started: Thu Feb 21 19:53:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shuzibiao -c shuzibiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shuzibiao -c shuzibiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.v" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bianma.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bianma.v" { { "Info" "ISGN_ENTITY_NAME" "1 bianma " "Info: Found entity 1: bianma" {  } { { "bianma.v" "" { Text "F:/clock_design/bianma.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LED.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LED.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED " "Info: Found entity 1: LED" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shuzibiao.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shuzibiao.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shuzibiao " "Info: Found entity 1: shuzibiao" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shuzibiao " "Info: Elaborating entity \"shuzibiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED LED:inst6 " "Info: Elaborating entity \"LED\" for hierarchy \"LED:inst6\"" {  } { { "shuzibiao.bdf" "inst6" { Schematic "F:/clock_design/shuzibiao.bdf" { { 216 664 816 344 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bianma bianma:inst " "Info: Elaborating entity \"bianma\" for hierarchy \"bianma:inst\"" {  } { { "shuzibiao.bdf" "inst" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 352 480 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "main main:inst1 " "Info: Elaborating entity \"main\" for hierarchy \"main:inst1\"" {  } { { "shuzibiao.bdf" "inst1" { Schematic "F:/clock_design/shuzibiao.bdf" { { 224 128 280 448 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(28) " "Warning (10230): Verilog HDL assignment warning at main.v(28): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(29) " "Warning (10230): Verilog HDL assignment warning at main.v(29): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(38) " "Warning (10230): Verilog HDL assignment warning at main.v(38): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(41) " "Warning (10230): Verilog HDL assignment warning at main.v(41): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(60) " "Warning (10230): Verilog HDL assignment warning at main.v(60): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(62) " "Warning (10230): Verilog HDL assignment warning at main.v(62): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(71) " "Warning (10230): Verilog HDL assignment warning at main.v(71): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(74) " "Warning (10230): Verilog HDL assignment warning at main.v(74): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "LED:inst6\|segout\[0\] High " "Info: Power-up level of register \"LED:inst6\|segout\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "LED:inst6\|segout\[0\] data_in VCC " "Warning: Reduced register \"LED:inst6\|segout\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|shuzibiao\|LED:inst6\|state 4 " "Info: State machine \"\|shuzibiao\|LED:inst6\|state\" contains 4 states" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|shuzibiao\|LED:inst6\|state " "Info: Selected Auto state machine encoding method for state machine \"\|shuzibiao\|LED:inst6\|state\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|shuzibiao\|LED:inst6\|state " "Info: Encoding result for state machine \"\|shuzibiao\|LED:inst6\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LED:inst6\|state.S1 " "Info: Encoded state bit \"LED:inst6\|state.S1\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LED:inst6\|state.S3 " "Info: Encoded state bit \"LED:inst6\|state.S3\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LED:inst6\|state.S2 " "Info: Encoded state bit \"LED:inst6\|state.S2\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LED:inst6\|state.S0 " "Info: Encoded state bit \"LED:inst6\|state.S0\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shuzibiao\|LED:inst6\|state.S0 0000 " "Info: State \"\|shuzibiao\|LED:inst6\|state.S0\" uses code string \"0000\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shuzibiao\|LED:inst6\|state.S2 0011 " "Info: State \"\|shuzibiao\|LED:inst6\|state.S2\" uses code string \"0011\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shuzibiao\|LED:inst6\|state.S3 0101 " "Info: State \"\|shuzibiao\|LED:inst6\|state.S3\" uses code string \"0101\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shuzibiao\|LED:inst6\|state.S1 1001 " "Info: State \"\|shuzibiao\|LED:inst6\|state.S1\" uses code string \"1001\"" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "LED:inst6\|state.S2 LED:inst6\|bitout\[1\] " "Info: Duplicate register \"LED:inst6\|state.S2\" merged to single register \"LED:inst6\|bitout\[1\]\", power-up level changed" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "LED:inst6\|state.S1 LED:inst6\|bitout\[0\] " "Info: Duplicate register \"LED:inst6\|state.S1\" merged to single register \"LED:inst6\|bitout\[0\]\", power-up level changed" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "segout\[0\] VCC " "Warning: Pin \"segout\[0\]\" stuck at VCC" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 240 848 1024 256 "segout\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "177 " "Info: Implemented 177 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "151 " "Info: Implemented 151 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 21 19:53:50 2008 " "Info: Processing ended: Thu Feb 21 19:53:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}