shuzibiao.fnsim.qmsg

数字钟的verilog代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 21 19:55:01 2008 " "Info: Processing started: Thu Feb 21 19:55:01 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shuzibiao -c shuzibiao --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shuzibiao -c shuzibiao --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.v" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bianma.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bianma.v" { { "Info" "ISGN_ENTITY_NAME" "1 bianma " "Info: Found entity 1: bianma" {  } { { "bianma.v" "" { Text "F:/clock_design/bianma.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LED.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LED.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED " "Info: Found entity 1: LED" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shuzibiao.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shuzibiao.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shuzibiao " "Info: Found entity 1: shuzibiao" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shuzibiao " "Info: Elaborating entity \"shuzibiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED LED:inst6 " "Info: Elaborating entity \"LED\" for hierarchy \"LED:inst6\"" {  } { { "shuzibiao.bdf" "inst6" { Schematic "F:/clock_design/shuzibiao.bdf" { { 216 664 816 344 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bianma bianma:inst " "Info: Elaborating entity \"bianma\" for hierarchy \"bianma:inst\"" {  } { { "shuzibiao.bdf" "inst" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 352 480 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "main main:inst1 " "Info: Elaborating entity \"main\" for hierarchy \"main:inst1\"" {  } { { "shuzibiao.bdf" "inst1" { Schematic "F:/clock_design/shuzibiao.bdf" { { 224 128 280 448 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(28) " "Warning (10230): Verilog HDL assignment warning at main.v(28): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(29) " "Warning (10230): Verilog HDL assignment warning at main.v(29): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(38) " "Warning (10230): Verilog HDL assignment warning at main.v(38): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(41) " "Warning (10230): Verilog HDL assignment warning at main.v(41): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(60) " "Warning (10230): Verilog HDL assignment warning at main.v(60): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(62) " "Warning (10230): Verilog HDL assignment warning at main.v(62): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(71) " "Warning (10230): Verilog HDL assignment warning at main.v(71): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 main.v(74) " "Warning (10230): Verilog HDL assignment warning at main.v(74): truncated value with size 32 to match size of target (4)" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}