shuzibiao.tan.qmsg

数字钟的verilog代码

{ "Info" "ITDB_TH_RESULT" "main:inst1\|L4\[1\] LD4 clk1 -2.192 ns register " "Info: th for register \"main:inst1\|L4\[1\]\" (data pin = \"LD4\", clock pin = \"clk1\") is -2.192 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.969 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk1 1 CLK PIN_M21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 17; CLK Node = 'clk1'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 248 -56 112 264 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.702 ns) + CELL(0.542 ns) 2.969 ns main:inst1\|L4\[1\] 2 REG LC_X35_Y18_N7 5 " "Info: 2: + IC(1.702 ns) + CELL(0.542 ns) = 2.969 ns; Loc. = LC_X35_Y18_N7; Fanout = 5; REG Node = 'main:inst1\|L4\[1\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.244 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.67 % ) " "Info: Total cell delay = 1.267 ns ( 42.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.702 ns ( 57.33 % ) " "Info: Total interconnect delay = 1.702 ns ( 57.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.261 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns LD4 1 PIN PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L1; Fanout = 4; PIN Node = 'LD4'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LD4 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 376 -56 112 392 "LD4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.458 ns) 5.261 ns main:inst1\|L4\[1\] 2 REG LC_X35_Y18_N7 5 " "Info: 2: + IC(4.078 ns) + CELL(0.458 ns) = 5.261 ns; Loc. = LC_X35_Y18_N7; Fanout = 5; REG Node = 'main:inst1\|L4\[1\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.536 ns" { LD4 main:inst1|L4[1] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.183 ns ( 22.49 % ) " "Info: Total cell delay = 1.183 ns ( 22.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.078 ns ( 77.51 % ) " "Info: Total interconnect delay = 4.078 ns ( 77.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { LD4 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { LD4 LD4~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 4.078ns } { 0.000ns 0.725ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { LD4 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { LD4 LD4~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 4.078ns } { 0.000ns 0.725ns 0.458ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 21 19:54:35 2008 " "Info: Processing ended: Thu Feb 21 19:54:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}