shuzibiao.tan.qmsg

数字钟的verilog代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register main:inst1\|L4\[1\] register main:inst1\|L4\[2\] 299.4 MHz 3.34 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 299.4 MHz between source register \"main:inst1\|L4\[1\]\" and destination register \"main:inst1\|L4\[2\]\" (period= 3.34 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.174 ns + Longest register register " "Info: + Longest register to register delay is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:inst1\|L4\[1\] 1 REG LC_X35_Y18_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y18_N7; Fanout = 5; REG Node = 'main:inst1\|L4\[1\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { main:inst1|L4[1] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.366 ns) 0.766 ns main:inst1\|L3\[3\]~1130 2 COMB LC_X35_Y18_N1 6 " "Info: 2: + IC(0.400 ns) + CELL(0.366 ns) = 0.766 ns; Loc. = LC_X35_Y18_N1; Fanout = 6; COMB Node = 'main:inst1\|L3\[3\]~1130'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.766 ns" { main:inst1|L4[1] main:inst1|L3[3]~1130 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.183 ns) 1.941 ns main:inst1\|L4\[2\]~723 3 COMB LC_X36_Y17_N3 2 " "Info: 3: + IC(0.992 ns) + CELL(0.183 ns) = 1.941 ns; Loc. = LC_X36_Y17_N3; Fanout = 2; COMB Node = 'main:inst1\|L4\[2\]~723'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.175 ns" { main:inst1|L3[3]~1130 main:inst1|L4[2]~723 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.010 ns) + CELL(0.223 ns) 3.174 ns main:inst1\|L4\[2\] 4 REG LC_X35_Y18_N5 4 " "Info: 4: + IC(1.010 ns) + CELL(0.223 ns) = 3.174 ns; Loc. = LC_X35_Y18_N5; Fanout = 4; REG Node = 'main:inst1\|L4\[2\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.233 ns" { main:inst1|L4[2]~723 main:inst1|L4[2] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.772 ns ( 24.32 % ) " "Info: Total cell delay = 0.772 ns ( 24.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.402 ns ( 75.68 % ) " "Info: Total interconnect delay = 2.402 ns ( 75.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { main:inst1|L4[1] main:inst1|L3[3]~1130 main:inst1|L4[2]~723 main:inst1|L4[2] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { main:inst1|L4[1] main:inst1|L3[3]~1130 main:inst1|L4[2]~723 main:inst1|L4[2] } { 0.000ns 0.400ns 0.992ns 1.010ns } { 0.000ns 0.366ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.969 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk1 1 CLK PIN_M21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 17; CLK Node = 'clk1'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 248 -56 112 264 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.702 ns) + CELL(0.542 ns) 2.969 ns main:inst1\|L4\[2\] 2 REG LC_X35_Y18_N5 4 " "Info: 2: + IC(1.702 ns) + CELL(0.542 ns) = 2.969 ns; Loc. = LC_X35_Y18_N5; Fanout = 4; REG Node = 'main:inst1\|L4\[2\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.244 ns" { clk1 main:inst1|L4[2] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.67 % ) " "Info: Total cell delay = 1.267 ns ( 42.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.702 ns ( 57.33 % ) " "Info: Total interconnect delay = 1.702 ns ( 57.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[2] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[2] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.969 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk1 1 CLK PIN_M21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 17; CLK Node = 'clk1'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 248 -56 112 264 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.702 ns) + CELL(0.542 ns) 2.969 ns main:inst1\|L4\[1\] 2 REG LC_X35_Y18_N7 5 " "Info: 2: + IC(1.702 ns) + CELL(0.542 ns) = 2.969 ns; Loc. = LC_X35_Y18_N7; Fanout = 5; REG Node = 'main:inst1\|L4\[1\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.244 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.67 % ) " "Info: Total cell delay = 1.267 ns ( 42.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.702 ns ( 57.33 % ) " "Info: Total interconnect delay = 1.702 ns ( 57.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[2] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[2] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { main:inst1|L4[1] main:inst1|L3[3]~1130 main:inst1|L4[2]~723 main:inst1|L4[2] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { main:inst1|L4[1] main:inst1|L3[3]~1130 main:inst1|L4[2]~723 main:inst1|L4[2] } { 0.000ns 0.400ns 0.992ns 1.010ns } { 0.000ns 0.366ns 0.183ns 0.223ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[2] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[2] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk1 main:inst1|L4[1] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk1 clk1~out0 main:inst1|L4[1] } { 0.000ns 0.000ns 1.702ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "main:inst1\|L1\[0\] data_in\[0\] clk1 6.810 ns register " "Info: tsu for register \"main:inst1\|L1\[0\]\" (data pin = \"data_in\[0\]\", clock pin = \"clk1\") is 6.810 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.762 ns + Longest pin register " "Info: + Longest pin to register delay is 9.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns data_in\[0\] 1 PIN PIN_T9 6 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T9; Fanout = 6; PIN Node = 'data_in\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_in[0] } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 392 -56 112 408 "data_in\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.738 ns) + CELL(0.183 ns) 6.008 ns main:inst1\|LessThan0~32 2 COMB LC_X36_Y17_N1 1 " "Info: 2: + IC(4.738 ns) + CELL(0.183 ns) = 6.008 ns; Loc. = LC_X36_Y17_N1; Fanout = 1; COMB Node = 'main:inst1\|LessThan0~32'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.921 ns" { data_in[0] main:inst1|LessThan0~32 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.310 ns) + CELL(0.280 ns) 6.598 ns main:inst1\|always0~0 3 COMB LC_X36_Y17_N5 3 " "Info: 3: + IC(0.310 ns) + CELL(0.280 ns) = 6.598 ns; Loc. = LC_X36_Y17_N5; Fanout = 3; COMB Node = 'main:inst1\|always0~0'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.590 ns" { main:inst1|LessThan0~32 main:inst1|always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.957 ns) + CELL(0.366 ns) 7.921 ns main:inst1\|L1\[0\]~611 4 COMB LC_X35_Y16_N9 1 " "Info: 4: + IC(0.957 ns) + CELL(0.366 ns) = 7.921 ns; Loc. = LC_X35_Y16_N9; Fanout = 1; COMB Node = 'main:inst1\|L1\[0\]~611'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.323 ns" { main:inst1|always0~0 main:inst1|L1[0]~611 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.505 ns) + CELL(0.280 ns) 8.706 ns main:inst1\|L1\[0\]~612 5 COMB LC_X34_Y16_N8 4 " "Info: 5: + IC(0.505 ns) + CELL(0.280 ns) = 8.706 ns; Loc. = LC_X34_Y16_N8; Fanout = 4; COMB Node = 'main:inst1\|L1\[0\]~612'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.785 ns" { main:inst1|L1[0]~611 main:inst1|L1[0]~612 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.705 ns) 9.762 ns main:inst1\|L1\[0\] 6 REG LC_X34_Y16_N2 6 " "Info: 6: + IC(0.351 ns) + CELL(0.705 ns) = 9.762 ns; Loc. = LC_X34_Y16_N2; Fanout = 6; REG Node = 'main:inst1\|L1\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.056 ns" { main:inst1|L1[0]~612 main:inst1|L1[0] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.901 ns ( 29.72 % ) " "Info: Total cell delay = 2.901 ns ( 29.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.861 ns ( 70.28 % ) " "Info: Total interconnect delay = 6.861 ns ( 70.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.762 ns" { data_in[0] main:inst1|LessThan0~32 main:inst1|always0~0 main:inst1|L1[0]~611 main:inst1|L1[0]~612 main:inst1|L1[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "9.762 ns" { data_in[0] data_in[0]~out0 main:inst1|LessThan0~32 main:inst1|always0~0 main:inst1|L1[0]~611 main:inst1|L1[0]~612 main:inst1|L1[0] } { 0.000ns 0.000ns 4.738ns 0.310ns 0.957ns 0.505ns 0.351ns } { 0.000ns 1.087ns 0.183ns 0.280ns 0.366ns 0.280ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk1 1 CLK PIN_M21 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 17; CLK Node = 'clk1'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 248 -56 112 264 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(0.542 ns) 2.962 ns main:inst1\|L1\[0\] 2 REG LC_X34_Y16_N2 6 " "Info: 2: + IC(1.695 ns) + CELL(0.542 ns) = 2.962 ns; Loc. = LC_X34_Y16_N2; Fanout = 6; REG Node = 'main:inst1\|L1\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.237 ns" { clk1 main:inst1|L1[0] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.78 % ) " "Info: Total cell delay = 1.267 ns ( 42.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.695 ns ( 57.22 % ) " "Info: Total interconnect delay = 1.695 ns ( 57.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk1 main:inst1|L1[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk1 clk1~out0 main:inst1|L1[0] } { 0.000ns 0.000ns 1.695ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.762 ns" { data_in[0] main:inst1|LessThan0~32 main:inst1|always0~0 main:inst1|L1[0]~611 main:inst1|L1[0]~612 main:inst1|L1[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "9.762 ns" { data_in[0] data_in[0]~out0 main:inst1|LessThan0~32 main:inst1|always0~0 main:inst1|L1[0]~611 main:inst1|L1[0]~612 main:inst1|L1[0] } { 0.000ns 0.000ns 4.738ns 0.310ns 0.957ns 0.505ns 0.351ns } { 0.000ns 1.087ns 0.183ns 0.280ns 0.366ns 0.280ns 0.705ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk1 main:inst1|L1[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk1 clk1~out0 main:inst1|L1[0] } { 0.000ns 0.000ns 1.695ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk3 bitout\[0\] LED:inst6\|bitout\[0\] 8.127 ns register " "Info: tco from clock \"clk3\" to destination pin \"bitout\[0\]\" through register \"LED:inst6\|bitout\[0\]\" is 8.127 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk3 source 3.044 ns + Longest register " "Info: + Longest clock path from clock \"clk3\" to source register is 3.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk3 1 CLK PIN_L20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 13; CLK Node = 'clk3'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 488 656 128 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.542 ns) 3.044 ns LED:inst6\|bitout\[0\] 2 REG LC_X35_Y15_N0 3 " "Info: 2: + IC(1.674 ns) + CELL(0.542 ns) = 3.044 ns; Loc. = LC_X35_Y15_N0; Fanout = 3; REG Node = 'LED:inst6\|bitout\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.216 ns" { clk3 LED:inst6|bitout[0] } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.01 % ) " "Info: Total cell delay = 1.370 ns ( 45.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 54.99 % ) " "Info: Total interconnect delay = 1.674 ns ( 54.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|bitout[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|bitout[0] } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.927 ns + Longest register pin " "Info: + Longest register to pin delay is 4.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED:inst6\|bitout\[0\] 1 REG LC_X35_Y15_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y15_N0; Fanout = 3; REG Node = 'LED:inst6\|bitout\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LED:inst6|bitout[0] } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.523 ns) + CELL(2.404 ns) 4.927 ns bitout\[0\] 2 PIN PIN_Y9 0 " "Info: 2: + IC(2.523 ns) + CELL(2.404 ns) = 4.927 ns; Loc. = PIN_Y9; Fanout = 0; PIN Node = 'bitout\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.927 ns" { LED:inst6|bitout[0] bitout[0] } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 256 848 1024 272 "bitout\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 48.79 % ) " "Info: Total cell delay = 2.404 ns ( 48.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.523 ns ( 51.21 % ) " "Info: Total interconnect delay = 2.523 ns ( 51.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.927 ns" { LED:inst6|bitout[0] bitout[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "4.927 ns" { LED:inst6|bitout[0] bitout[0] } { 0.000ns 2.523ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|bitout[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|bitout[0] } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.927 ns" { LED:inst6|bitout[0] bitout[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "4.927 ns" { LED:inst6|bitout[0] bitout[0] } { 0.000ns 2.523ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}