shuzibiao.tan.qmsg

数字钟的verilog代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk3 " "Info: Assuming node \"clk3\" is an undefined clock" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 488 656 128 "clk3" "" } } } } { "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 264 -56 112 280 "clk2" "" } } } } { "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 248 -56 112 264 "clk1" "" } } } } { "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/ruanjian/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk3 register LED:inst6\|state.S3 register LED:inst6\|segout\[4\] 373.97 MHz 2.674 ns Internal " "Info: Clock \"clk3\" has Internal fmax of 373.97 MHz between source register \"LED:inst6\|state.S3\" and destination register \"LED:inst6\|segout\[4\]\" (period= 2.674 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.508 ns + Longest register register " "Info: + Longest register to register delay is 2.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED:inst6\|state.S3 1 REG LC_X35_Y15_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y15_N5; Fanout = 4; REG Node = 'LED:inst6\|state.S3'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LED:inst6|state.S3 } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.280 ns) 0.660 ns LED:inst6\|segout\[7\]~39 2 COMB LC_X35_Y15_N4 11 " "Info: 2: + IC(0.380 ns) + CELL(0.280 ns) = 0.660 ns; Loc. = LC_X35_Y15_N4; Fanout = 11; COMB Node = 'LED:inst6\|segout\[7\]~39'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.660 ns" { LED:inst6|state.S3 LED:inst6|segout[7]~39 } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.183 ns) 1.767 ns LED:inst6\|Selector3~13 3 COMB LC_X35_Y15_N8 1 " "Info: 3: + IC(0.924 ns) + CELL(0.183 ns) = 1.767 ns; Loc. = LC_X35_Y15_N8; Fanout = 1; COMB Node = 'LED:inst6\|Selector3~13'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.107 ns" { LED:inst6|segout[7]~39 LED:inst6|Selector3~13 } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.223 ns) 2.508 ns LED:inst6\|segout\[4\] 4 REG LC_X36_Y15_N7 1 " "Info: 4: + IC(0.518 ns) + CELL(0.223 ns) = 2.508 ns; Loc. = LC_X36_Y15_N7; Fanout = 1; REG Node = 'LED:inst6\|segout\[4\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { LED:inst6|Selector3~13 LED:inst6|segout[4] } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.686 ns ( 27.35 % ) " "Info: Total cell delay = 0.686 ns ( 27.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.822 ns ( 72.65 % ) " "Info: Total interconnect delay = 1.822 ns ( 72.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.508 ns" { LED:inst6|state.S3 LED:inst6|segout[7]~39 LED:inst6|Selector3~13 LED:inst6|segout[4] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.508 ns" { LED:inst6|state.S3 LED:inst6|segout[7]~39 LED:inst6|Selector3~13 LED:inst6|segout[4] } { 0.000ns 0.380ns 0.924ns 0.518ns } { 0.000ns 0.280ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk3 destination 3.044 ns + Shortest register " "Info: + Shortest clock path from clock \"clk3\" to destination register is 3.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk3 1 CLK PIN_L20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 13; CLK Node = 'clk3'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 488 656 128 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.542 ns) 3.044 ns LED:inst6\|segout\[4\] 2 REG LC_X36_Y15_N7 1 " "Info: 2: + IC(1.674 ns) + CELL(0.542 ns) = 3.044 ns; Loc. = LC_X36_Y15_N7; Fanout = 1; REG Node = 'LED:inst6\|segout\[4\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.216 ns" { clk3 LED:inst6|segout[4] } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.01 % ) " "Info: Total cell delay = 1.370 ns ( 45.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 54.99 % ) " "Info: Total interconnect delay = 1.674 ns ( 54.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|segout[4] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|segout[4] } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk3 source 3.044 ns - Longest register " "Info: - Longest clock path from clock \"clk3\" to source register is 3.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk3 1 CLK PIN_L20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 13; CLK Node = 'clk3'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk3 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 112 488 656 128 "clk3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.542 ns) 3.044 ns LED:inst6\|state.S3 2 REG LC_X35_Y15_N5 4 " "Info: 2: + IC(1.674 ns) + CELL(0.542 ns) = 3.044 ns; Loc. = LC_X35_Y15_N5; Fanout = 4; REG Node = 'LED:inst6\|state.S3'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.216 ns" { clk3 LED:inst6|state.S3 } "NODE_NAME" } } { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.01 % ) " "Info: Total cell delay = 1.370 ns ( 45.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 54.99 % ) " "Info: Total interconnect delay = 1.674 ns ( 54.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|state.S3 } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|state.S3 } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|segout[4] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|segout[4] } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|state.S3 } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|state.S3 } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "LED.v" "" { Text "F:/clock_design/LED.v" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.508 ns" { LED:inst6|state.S3 LED:inst6|segout[7]~39 LED:inst6|Selector3~13 LED:inst6|segout[4] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "2.508 ns" { LED:inst6|state.S3 LED:inst6|segout[7]~39 LED:inst6|Selector3~13 LED:inst6|segout[4] } { 0.000ns 0.380ns 0.924ns 0.518ns } { 0.000ns 0.280ns 0.183ns 0.223ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|segout[4] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|segout[4] } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.044 ns" { clk3 LED:inst6|state.S3 } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.044 ns" { clk3 clk3~out0 LED:inst6|state.S3 } { 0.000ns 0.000ns 1.674ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk2 register main:inst1\|P4\[0\] register main:inst1\|P3\[3\] 294.55 MHz 3.395 ns Internal " "Info: Clock \"clk2\" has Internal fmax of 294.55 MHz between source register \"main:inst1\|P4\[0\]\" and destination register \"main:inst1\|P3\[3\]\" (period= 3.395 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.229 ns + Longest register register " "Info: + Longest register to register delay is 3.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:inst1\|P4\[0\] 1 REG LC_X34_Y18_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y18_N3; Fanout = 5; REG Node = 'main:inst1\|P4\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { main:inst1|P4[0] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.366 ns) 0.792 ns main:inst1\|Equal7~115 2 COMB LC_X34_Y18_N7 7 " "Info: 2: + IC(0.426 ns) + CELL(0.366 ns) = 0.792 ns; Loc. = LC_X34_Y18_N7; Fanout = 7; COMB Node = 'main:inst1\|Equal7~115'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.792 ns" { main:inst1|P4[0] main:inst1|Equal7~115 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.183 ns) 1.965 ns main:inst1\|P3~399 3 COMB LC_X34_Y17_N4 3 " "Info: 3: + IC(0.990 ns) + CELL(0.183 ns) = 1.965 ns; Loc. = LC_X34_Y17_N4; Fanout = 3; COMB Node = 'main:inst1\|P3~399'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.173 ns" { main:inst1|Equal7~115 main:inst1|P3~399 } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.223 ns) 3.229 ns main:inst1\|P3\[3\] 4 REG LC_X34_Y18_N5 3 " "Info: 4: + IC(1.041 ns) + CELL(0.223 ns) = 3.229 ns; Loc. = LC_X34_Y18_N5; Fanout = 3; REG Node = 'main:inst1\|P3\[3\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.264 ns" { main:inst1|P3~399 main:inst1|P3[3] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.772 ns ( 23.91 % ) " "Info: Total cell delay = 0.772 ns ( 23.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.457 ns ( 76.09 % ) " "Info: Total interconnect delay = 2.457 ns ( 76.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.229 ns" { main:inst1|P4[0] main:inst1|Equal7~115 main:inst1|P3~399 main:inst1|P3[3] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.229 ns" { main:inst1|P4[0] main:inst1|Equal7~115 main:inst1|P3~399 main:inst1|P3[3] } { 0.000ns 0.426ns 0.990ns 1.041ns } { 0.000ns 0.366ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 3.029 ns + Shortest register " "Info: + Shortest clock path from clock \"clk2\" to destination register is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk2 1 CLK PIN_M20 33 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 33; CLK Node = 'clk2'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 264 -56 112 280 "clk2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 3.029 ns main:inst1\|P3\[3\] 2 REG LC_X34_Y18_N5 3 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 3.029 ns; Loc. = LC_X34_Y18_N5; Fanout = 3; REG Node = 'main:inst1\|P3\[3\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.201 ns" { clk2 main:inst1|P3[3] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.23 % ) " "Info: Total cell delay = 1.370 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns ( 54.77 % ) " "Info: Total interconnect delay = 1.659 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P3[3] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P3[3] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 3.029 ns - Longest register " "Info: - Longest clock path from clock \"clk2\" to source register is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk2 1 CLK PIN_M20 33 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 33; CLK Node = 'clk2'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "shuzibiao.bdf" "" { Schematic "F:/clock_design/shuzibiao.bdf" { { 264 -56 112 280 "clk2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 3.029 ns main:inst1\|P4\[0\] 2 REG LC_X34_Y18_N3 5 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 3.029 ns; Loc. = LC_X34_Y18_N3; Fanout = 5; REG Node = 'main:inst1\|P4\[0\]'" {  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.201 ns" { clk2 main:inst1|P4[0] } "NODE_NAME" } } { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.23 % ) " "Info: Total cell delay = 1.370 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns ( 54.77 % ) " "Info: Total interconnect delay = 1.659 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P4[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P4[0] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P3[3] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P3[3] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P4[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P4[0] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "main.v" "" { Text "F:/clock_design/main.v" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.229 ns" { main:inst1|P4[0] main:inst1|Equal7~115 main:inst1|P3~399 main:inst1|P3[3] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.229 ns" { main:inst1|P4[0] main:inst1|Equal7~115 main:inst1|P3~399 main:inst1|P3[3] } { 0.000ns 0.426ns 0.990ns 1.041ns } { 0.000ns 0.366ns 0.183ns 0.223ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P3[3] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P3[3] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/ruanjian/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.029 ns" { clk2 main:inst1|P4[0] } "NODE_NAME" } } { "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/ruanjian/altera/quartus60/win/Technology_Viewer.qrui" "3.029 ns" { clk2 clk2~out0 main:inst1|P4[0] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}