led.v

数字钟的verilog代码

module LED(clk3,segout,bitout,D1,D2,D3,D4);

input clk3;
input [7:0]D1,D2,D3,D4;


output [7:0] segout;
output [3:0] bitout;

reg [7:0] segout;
reg [3:0] bitout;
reg [1:0] state;

parameter S0=2'b00,           
          S1=2'b01,
          S2=2'b10,
          S3=2'b11;
          
always@(posedge clk3)
 begin
     case(state)
     S0:                                 
        begin
             segout <=D1;
             bitout <=4'b1110;
             state<=S1;
        end
     S1:                             
        begin
             segout <=D2;
             bitout <=4'b1101;
             state<=S2;
        end
     S2:                               
        begin
             segout <=D3;
             bitout <=4'b1011;
             state<=S3;
        end
     S3:                                  
       begin
            segout <=D4;
            bitout <=4'b0111;
       end
     default: state<=S0;   
     endcase
 end

endmodule