📄 shuzibiao.map.rpt
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; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 63 ;
; I/O pins ; 26 ;
; Maximum fan-out node ; clk2 ;
; Maximum fan-out ; 33 ;
; Total fan-out ; 632 ;
; Average fan-out ; 3.57 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; |shuzibiao ; 151 (0) ; 63 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 88 (0) ; 2 (0) ; 61 (0) ; 0 (0) ; 0 (0) ; |shuzibiao ;
; |LED:inst6| ; 22 (22) ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 2 (2) ; 11 (11) ; 0 (0) ; 0 (0) ; |shuzibiao|LED:inst6 ;
; |bianma:inst3| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |shuzibiao|bianma:inst3 ;
; |bianma:inst4| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |shuzibiao|bianma:inst4 ;
; |bianma:inst5| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |shuzibiao|bianma:inst5 ;
; |bianma:inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |shuzibiao|bianma:inst ;
; |main:inst1| ; 101 (101) ; 50 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 51 (51) ; 0 (0) ; 50 (50) ; 0 (0) ; 0 (0) ; |shuzibiao|main:inst1 ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; State Machine - |shuzibiao|LED:inst6|state ;
+----------+----------+----------+----------+----------+
; Name ; state.S1 ; state.S3 ; state.S2 ; state.S0 ;
+----------+----------+----------+----------+----------+
; state.S0 ; 0 ; 0 ; 0 ; 0 ;
; state.S2 ; 0 ; 0 ; 1 ; 1 ;
; state.S3 ; 0 ; 1 ; 0 ; 1 ;
; state.S1 ; 1 ; 0 ; 0 ; 1 ;
+----------+----------+----------+----------+----------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 63 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 32 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; LED:inst6|bitout[1] ; 4 ;
; LED:inst6|bitout[0] ; 3 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|P2[0] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|P4[3] ;
; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |shuzibiao|LED:inst6|segout[7] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|L4[2] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|P1[2] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|P3[3] ;
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |shuzibiao|main:inst1|L2[3] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|L3[3] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |shuzibiao|main:inst1|L1[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: LED:inst6 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; S0 ; 00 ; Binary ;
; S1 ; 01 ; Binary ;
; S2 ; 10 ; Binary ;
; S3 ; 11 ; Binary ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Feb 21 19:53:45 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shuzibiao -c shuzibiao
Info: Found 1 design units, including 1 entities, in source file main.v
Info: Found entity 1: main
Info: Found 1 design units, including 1 entities, in source file bianma.v
Info: Found entity 1: bianma
Info: Found 1 design units, including 1 entities, in source file LED.v
Info: Found entity 1: LED
Info: Found 1 design units, including 1 entities, in source file shuzibiao.bdf
Info: Found entity 1: shuzibiao
Info: Elaborating entity "shuzibiao" for the top level hierarchy
Info: Elaborating entity "LED" for hierarchy "LED:inst6"
Info: Elaborating entity "bianma" for hierarchy "bianma:inst"
Info: Elaborating entity "main" for hierarchy "main:inst1"
Warning (10230): Verilog HDL assignment warning at main.v(28): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(29): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(38): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(41): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(60): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(62): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(71): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at main.v(74): truncated value with size 32 to match size of target (4)
Info: Power-up level of register "LED:inst6|segout[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "LED:inst6|segout[0]" with stuck data_in port to stuck value VCC
Info: State machine "|shuzibiao|LED:inst6|state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|shuzibiao|LED:inst6|state"
Info: Encoding result for state machine "|shuzibiao|LED:inst6|state"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "LED:inst6|state.S1"
Info: Encoded state bit "LED:inst6|state.S3"
Info: Encoded state bit "LED:inst6|state.S2"
Info: Encoded state bit "LED:inst6|state.S0"
Info: State "|shuzibiao|LED:inst6|state.S0" uses code string "0000"
Info: State "|shuzibiao|LED:inst6|state.S2" uses code string "0011"
Info: State "|shuzibiao|LED:inst6|state.S3" uses code string "0101"
Info: State "|shuzibiao|LED:inst6|state.S1" uses code string "1001"
Info: Duplicate registers merged to single register
Info: Duplicate register "LED:inst6|state.S2" merged to single register "LED:inst6|bitout[1]", power-up level changed
Info: Duplicate register "LED:inst6|state.S1" merged to single register "LED:inst6|bitout[0]", power-up level changed
Warning: Output pins are stuck at VCC or GND
Warning: Pin "segout[0]" stuck at VCC
Info: Implemented 177 device resources after synthesis - the final resource count might be different
Info: Implemented 14 input pins
Info: Implemented 12 output pins
Info: Implemented 151 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Processing ended: Thu Feb 21 19:53:50 2008
Info: Elapsed time: 00:00:07
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