seltime.rpt

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Project Information                                     k:\timevhd\seltime.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/14/2005 22:23:46

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


SELTIME


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

seltime   EPM7032SLC44-5   22       7        0      7       12          21 %

User Pins:                 22       7        0  



Project Information                                     k:\timevhd\seltime.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clk' chosen for auto global Clock
INFO: Signal 'reset' chosen for auto global Clear


Project Information                                     k:\timevhd\seltime.rpt

** FILE HIERARCHY **



|lpm_add_sub:46|
|lpm_add_sub:46|addcore:adder|
|lpm_add_sub:46|addcore:adder|addcore:adder0|
|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

***** Logic for device 'seltime' compiled without errors.




Device: EPM7032SLC44-5

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff



Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** ERROR SUMMARY **

Info: Chip 'seltime' in device 'EPM7032SLC44-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                               
                                               
                                               
              h  h  h        r                 
              o  o  o        e           m  m  
              u  u  u  V  G  s  G  c  G  i  i  
              r  r  r  C  N  e  N  l  N  n  n  
              3  4  5  C  D  t  D  k  D  5  6  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | sel0 
   hour2 |  8                                38 | #TDO 
   hour1 |  9                                37 | sec3 
     GND | 10                                36 | sec0 
   hour0 | 11                                35 | VCC 
    min1 | 12         EPM7032SLC44-5         34 | sel2 
    #TMS | 13                                33 | sel1 
    min2 | 14                                32 | #TCK 
     VCC | 15                                31 | daout2 
    min3 | 16                                30 | GND 
    min0 | 17                                29 | sec1 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              m  s  s  s  G  V  R  d  d  d  s  
              i  e  e  e  N  C  E  a  a  a  e  
              n  c  c  c  D  C  S  o  o  o  c  
              4  6  5  4        E  u  u  u  2  
                                R  t  t  t     
                                V  1  3  0     
                                E              
                                D              


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)  16/16(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     7/16( 43%)  15/16( 93%)  15/16( 93%)  23/36( 63%) 


Total dedicated input pins used:                 2/4      ( 50%)
Total I/O pins used:                            31/32     ( 96%)
Total logic cells used:                          7/32     ( 21%)
Total shareable expanders used:                 12/32     ( 37%)
Total Turbo logic cells used:                    7/32     ( 21%)
Total shareable expanders not available (n/a):   3/32     (  9%)
Average fan-in:                                  6.28
Total fan-in:                                    44

Total input pins required:                      22
Total fast input logic cells required:           0
Total output pins required:                      7
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                      7
Total flipflops required:                        3
Total product terms required:                   33
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          12

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  43      -   -       INPUT  G            0      0   0    0    0    0    0  clk
  11    (7)  (A)      INPUT               0      0   0    0    0    1    0  hour0
   9    (6)  (A)      INPUT               0      0   0    0    0    1    0  hour1
   8    (5)  (A)      INPUT               0      0   0    0    0    1    0  hour2
   6    (3)  (A)      INPUT               0      0   0    0    0    1    0  hour3
   5    (2)  (A)      INPUT               0      0   0    0    0    1    0  hour4
   4    (1)  (A)      INPUT               0      0   0    0    0    1    0  hour5
  17   (12)  (A)      INPUT               0      0   0    0    0    1    0  min0
  12    (8)  (A)      INPUT               0      0   0    0    0    1    0  min1
  14   (10)  (A)      INPUT               0      0   0    0    0    1    0  min2
  16   (11)  (A)      INPUT               0      0   0    0    0    1    0  min3
  18   (13)  (A)      INPUT               0      0   0    0    0    1    0  min4
  41   (17)  (B)      INPUT               0      0   0    0    0    1    0  min5
  40   (18)  (B)      INPUT               0      0   0    0    0    1    0  min6
   1      -   -       INPUT  G            0      0   0    0    0    0    0  reset
  36   (22)  (B)      INPUT               0      0   0    0    0    1    0  sec0
  29   (27)  (B)      INPUT               0      0   0    0    0    1    0  sec1
  28   (28)  (B)      INPUT               0      0   0    0    0    1    0  sec2
  37   (21)  (B)      INPUT               0      0   0    0    0    1    0  sec3
  21   (16)  (A)      INPUT               0      0   0    0    0    1    0  sec4
  20   (15)  (A)      INPUT               0      0   0    0    0    1    0  sec5
  19   (14)  (A)      INPUT               0      0   0    0    0    1    0  sec6


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  27     29    B     OUTPUT      t        6      1   1    6    3    0    0  daout0
  25     31    B     OUTPUT      t        6      1   1    6    3    0    0  daout1
  31     26    B     OUTPUT      t        5      1   1    5    3    0    0  daout2
  26     30    B     OUTPUT      t        0      0   0    3    3    0    0  daout3
  39     19    B         FF   +  t        0      0   0    0    0    6    0  sel0 (:42)
  33     24    B         FF   +  t        0      0   0    0    1    5    0  sel1 (:41)
  34     23    B         FF   +  t        0      0   0    0    2    4    0  sel2 (:40)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':