seltime.rpt

来自「个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真」· RPT 代码 · 共 513 行 · 第 1/2 页

                       Logic cells placed in LAB 'B'
        +------------- LC29 daout0
        | +----------- LC31 daout1
        | | +--------- LC26 daout2
        | | | +------- LC30 daout3
        | | | | +----- LC19 sel0
        | | | | | +--- LC24 sel1
        | | | | | | +- LC23 sel2
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC19 -> * * * * * * * | - * | <-- sel0
LC24 -> * * * * - * * | - * | <-- sel1
LC23 -> * * * * - - * | - * | <-- sel2

Pin
43   -> - - - - - - - | - - | <-- clk
11   -> * - - - - - - | - * | <-- hour0
9    -> - * - - - - - | - * | <-- hour1
8    -> - - * - - - - | - * | <-- hour2
6    -> - - - * - - - | - * | <-- hour3
5    -> * - - - - - - | - * | <-- hour4
4    -> - * - - - - - | - * | <-- hour5
17   -> * - - - - - - | - * | <-- min0
12   -> - * - - - - - | - * | <-- min1
14   -> - - * - - - - | - * | <-- min2
16   -> - - - * - - - | - * | <-- min3
18   -> * - - - - - - | - * | <-- min4
41   -> - * - - - - - | - * | <-- min5
40   -> - - * - - - - | - * | <-- min6
1    -> - - - - - - - | - - | <-- reset
36   -> * - - - - - - | - * | <-- sec0
29   -> - * - - - - - | - * | <-- sec1
28   -> - - * - - - - | - * | <-- sec2
37   -> - - - * - - - | - * | <-- sec3
21   -> * - - - - - - | - * | <-- sec4
20   -> - * - - - - - | - * | <-- sec5
19   -> - - * - - - - | - * | <-- sec6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            k:\timevhd\seltime.rpt
seltime

** EQUATIONS **

clk      : INPUT;
hour0    : INPUT;
hour1    : INPUT;
hour2    : INPUT;
hour3    : INPUT;
hour4    : INPUT;
hour5    : INPUT;
min0     : INPUT;
min1     : INPUT;
min2     : INPUT;
min3     : INPUT;
min4     : INPUT;
min5     : INPUT;
min6     : INPUT;
reset    : INPUT;
sec0     : INPUT;
sec1     : INPUT;
sec2     : INPUT;
sec3     : INPUT;
sec4     : INPUT;
sec5     : INPUT;
sec6     : INPUT;

-- Node name is 'daout0' 
-- Equation name is 'daout0', location is LC029, type is output.
 daout0  = LCELL( _EQ001 $  _EQ002);
  _EQ001 = !min0 & !min4 & !sec0 & !sec4 & !sel2 &  _X001 &  _X002 &  _X003 & 
              _X004 &  _X005
         # !hour0 & !hour4 & !sec0 & !sec4 & !sel1 &  _X001 &  _X002 &  _X003 & 
              _X004 &  _X005
         # !sec4 &  sel0 & !sel1 & !sel2 &  _X001 &  _X002 &  _X003 &  _X004 & 
              _X005
         # !sec0 & !sel0 & !sel1 & !sel2 &  _X001 &  _X002 &  _X003 &  _X004 & 
              _X005;
  _X001  = EXP(!hour4 &  sel0 &  sel2);
  _X002  = EXP( sel1 &  sel2);
  _X003  = EXP(!min4 &  sel0 &  sel1);
  _X004  = EXP(!hour0 & !sel0 &  sel2);
  _X005  = EXP(!min0 & !sel0 &  sel1);
  _EQ002 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005;
  _X001  = EXP(!hour4 &  sel0 &  sel2);
  _X002  = EXP( sel1 &  sel2);
  _X003  = EXP(!min4 &  sel0 &  sel1);
  _X004  = EXP(!hour0 & !sel0 &  sel2);
  _X005  = EXP(!min0 & !sel0 &  sel1);

-- Node name is 'daout1' 
-- Equation name is 'daout1', location is LC031, type is output.
 daout1  = LCELL( _EQ003 $  _EQ004);
  _EQ003 = !min1 & !min5 & !sec1 & !sec5 & !sel2 &  _X002 &  _X006 &  _X007 & 
              _X008 &  _X009
         # !hour1 & !hour5 & !sec1 & !sec5 & !sel1 &  _X002 &  _X006 &  _X007 & 
              _X008 &  _X009
         # !sec5 &  sel0 & !sel1 & !sel2 &  _X002 &  _X006 &  _X007 &  _X008 & 
              _X009
         # !sec1 & !sel0 & !sel1 & !sel2 &  _X002 &  _X006 &  _X007 &  _X008 & 
              _X009;
  _X002  = EXP( sel1 &  sel2);
  _X006  = EXP(!hour5 &  sel0 &  sel2);
  _X007  = EXP(!min5 &  sel0 &  sel1);
  _X008  = EXP(!hour1 & !sel0 &  sel2);
  _X009  = EXP(!min1 & !sel0 &  sel1);
  _EQ004 =  _X002 &  _X006 &  _X007 &  _X008 &  _X009;
  _X002  = EXP( sel1 &  sel2);
  _X006  = EXP(!hour5 &  sel0 &  sel2);
  _X007  = EXP(!min5 &  sel0 &  sel1);
  _X008  = EXP(!hour1 & !sel0 &  sel2);
  _X009  = EXP(!min1 & !sel0 &  sel1);

-- Node name is 'daout2' 
-- Equation name is 'daout2', location is LC026, type is output.
 daout2  = LCELL( _EQ005 $  _EQ006);
  _EQ005 = !min2 & !min6 & !sec2 & !sec6 & !sel2 &  _X002 &  _X010 &  _X011 & 
              _X012
         # !sec2 & !sel0 & !sel1 & !sel2 &  _X002 &  _X010 &  _X011 &  _X012
         # !min6 &  sel0 &  sel1 &  _X002 &  _X010 &  _X011 &  _X012
         # !sec6 &  sel0 & !sel1 &  _X002 &  _X010 &  _X011 &  _X012;
  _X002  = EXP( sel1 &  sel2);
  _X010  = EXP( sel0 &  sel2);
  _X011  = EXP(!min2 & !sel0 &  sel1);
  _X012  = EXP(!hour2 &  sel2);
  _EQ006 =  _X002 &  _X010 &  _X011 &  _X012;
  _X002  = EXP( sel1 &  sel2);
  _X010  = EXP( sel0 &  sel2);
  _X011  = EXP(!min2 & !sel0 &  sel1);
  _X012  = EXP(!hour2 &  sel2);

-- Node name is 'daout3' 
-- Equation name is 'daout3', location is LC030, type is output.
 daout3  = LCELL( _EQ007 $  GND);
  _EQ007 =  min3 & !sel0 &  sel1 & !sel2
         #  hour3 & !sel0 & !sel1 &  sel2
         #  sec3 & !sel0 & !sel1 & !sel2;

-- Node name is 'sel0' = 'tmpa0~122' 
-- Equation name is 'sel0', location is LC019, type is output.
 sel0    = TFFE( VCC, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);

-- Node name is 'sel1' = 'tmpa1~122' 
-- Equation name is 'sel1', location is LC024, type is output.
 sel1    = TFFE( sel0, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);

-- Node name is 'sel2' = 'tmpa2~122' 
-- Equation name is 'sel2', location is LC023, type is output.
 sel2    = TFFE( _EQ008, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ008 =  sel0 &  sel1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     k:\timevhd\seltime.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,334K