fourbitadder.vhd

用VHDL语言采用串行方法实现用1位全加器实现4位全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fourbitadder IS
	PORT(x,y:IN BIT_VECTOR(3 DOWNTO 0);
		sum:OUT BIT_VECTOR(3 DOWNTO 0);
		dcount:OUT BIT);
END fourbitadder;
ARCHITECTURE haver OF fourbitadder IS
	COMPONENT onebitadder
		PORT(x,y,cin:IN BIT;
			sum,count:OUT BIT);
	END COMPONENT;
SIGNAL d:BIT_VECTOR(0 TO 4);
	BEGIN
		d(0)<='1';
U0:onebitadder PORT	MAP(x(0),y(0),d(0),sum(0),d(1));
U1:onebitadder PORT	MAP(x(1),y(1),d(1),sum(1),d(2));
U2:onebitadder PORT	MAP(x(2),y(2),d(2),sum(2),d(3));
U3:onebitadder PORT	MAP(x(3),y(3),d(3),sum(3),d(4));
dcount<=d(4);
END haver;