fourbitadder.map.summary

来自「用VHDL语言采用串行方法实现用1位全加器实现4位全加器」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sat Apr 19 09:18:15 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : fourbitadder
Top-level Entity Name : fourbitadder
Family : Cyclone
Total logic elements : 7
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0