onebitadder.vhd

来自「用VHDL语言采用串行方法实现用1位全加器实现4位全加器」· VHDL 代码 · 共 11 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY onebitadder IS
  PORT(x,y,cin:IN BIT;
	   sum,count:OUT BIT);
END onebitadder;
ARCHITECTURE dataflow OF onebitadder IS
BEGIN
	sum<=x XOR y XOR cin;
	count<=(x AND y)OR(x AND cin)OR(y AND cin);
END dataflow;