top_ba.v

Core_PWM,verilog语言编写

    NOR2A \u0/un1_counter_0_I_51  (.A(\u0/clock_divide_r[27]_net_1 ), 
        .B(\u0/counter[27]_net_1 ), .Y(\u0/N_134_0 ));
    AO1C \u0/un1_counter_0_I_212  (.A(\u0/counter[8]_net_1 ), .B(
        \u0/clock_divide_r[8]_net_1 ), .C(\u0/N_35_0 ), .Y(\u0/N_40_1 )
        );
    AND2 \u0/un8_counter_I_220  (.A(\u0/DWACT_FINC_E[26] ), .B(
        \u0/counter[30]_net_1 ), .Y(\u0/DWACT_FINC_E[27] ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_8  (.A(\u0/duty_cycle_r[26]_net_1 ), 
        .B(\u0/counter[26]_net_1 ), .Y(\u0/DWACT_BL_EQUAL_0_E_0[7] ));
    AND3 \u0/un8_counter_I_189  (.A(\u0/counter[24]_net_1 ), .B(
        \u0/counter[25]_net_1 ), .C(\u0/counter[26]_net_1 ), .Y(
        \u0/DWACT_FINC_E[22] ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_3  (.A(\u0/duty_cycle_r[21]_net_1 ), 
        .B(\u0/counter[21]_net_1 ), .Y(\u0/DWACT_BL_EQUAL_0_E_4[2] ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_192  (.A(\u0/duty_cycle_r[5]_net_1 )
        , .B(\u0/counter[5]_net_1 ), .Y(\u0/DWACT_BL_EQUAL_0_E[0] ));
    AND3 \u0/un8_counter_I_135  (.A(\u0/DWACT_FINC_E[28] ), .B(
        \u0/DWACT_FINC_E[13] ), .C(\u0/DWACT_FINC_E[15] ), .Y(
        \u0/N_66 ));
    AO1 \u0/un1_counter_0_I_238  (.A(
        \u0/DWACT_CMPLE_PO2_DWACT_COMP0_E_3[1] ), .B(
        \u0/DWACT_CMPLE_PO2_DWACT_COMP0_E_3[2] ), .C(
        \u0/DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] ), .Y(
        \u0/DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] ));
    DFN1E0C1 \u0/duty_cycle_r[4]  (.D(\data[4] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_299_i ), .Q(\u0/duty_cycle_r[4]_net_1 ));
    DFN1E0C1 \u0/clock_divide_r[25]  (.D(\data[1] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_283_i ), .Q(\u0/clock_divide_r[25]_net_1 ));
    XNOR2 \u0/un1_counter_0_I_12  (.A(\u0/counter[30]_net_1 ), .B(
        \u0/clock_divide_r[30]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_0[11] ));
    AND3 \u0/un8_counter_I_87  (.A(\u0/counter[12]_net_1 ), .B(
        \u0/counter[13]_net_1 ), .C(\u0/counter[14]_net_1 ), .Y(
        \u0/DWACT_FINC_E[9] ));
    DFN1E0C1 \u0/clock_divide_r[16]  (.D(\data[0] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_267_i ), .Q(\u0/clock_divide_r[16]_net_1 ));
    DFN1E0C1 \u0/duty_cycle_r[26]  (.D(\data[2] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_347_i ), .Q(\u0/duty_cycle_r[26]_net_1 ));
    OR2A \u0/un1_counter_0_I_50  (.A(\u0/counter[29]_net_1 ), .B(
        \u0/clock_divide_r[29]_net_1 ), .Y(\u0/N_133_0 ));
    IOIN_IB \rst_pad/U0/U1  (.YIN(\rst_pad/U0/NET1 ), .Y(rst_pad));
    OR3A \u2/status_0_sqmuxa_1_0_a4_0_a3  (.A(\u2/status[0]_net_1 ), 
        .B(\u2/status[1]_net_1 ), .C(
        \u2/status_ns_1_iv_0_o2_0[0]_net_1 ), .Y(
        \u2/status_0_sqmuxa_1 ));
    AND3 \u0/un8_counter_I_90  (.A(\u0/DWACT_FINC_E[6] ), .B(
        \u0/DWACT_FINC_E[7] ), .C(\u0/DWACT_FINC_E[9] ), .Y(\u0/N_98 ));
    XNOR2 \u0/un1_counter_0_I_117  (.A(\u0/counter[13]_net_1 ), .B(
        \u0/clock_divide_r[13]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_6[3] ));
    OR2A \u0/un1_duty_cycle_r_0_I_205  (.A(\u0/duty_cycle_r[7]_net_1 ), 
        .B(\u0/counter[7]_net_1 ), .Y(\u0/N_33 ));
    DFN1C1 \u0/counter[21]  (.D(\u0/counter_5[21]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[21]_net_1 ));
    AND2 \u0/un8_counter_I_199  (.A(\u0/DWACT_FINC_E[29] ), .B(
        \u0/DWACT_FINC_E[30] ), .Y(\u0/DWACT_FINC_E[24] ));
    DFN1C1 \u0/counter[6]  (.D(\u0/counter_5[6]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[6]_net_1 ));
    DFN1C1 \u0/counter[27]  (.D(\u0/counter_5[27]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[27]_net_1 ));
    NOR2B \u0/counter_5[9]  (.A(\u0/I_52 ), .B(\u0/I_248 ), .Y(
        \u0/counter_5[9]_net_1 ));
    OR2A \u0/un1_duty_cycle_r_0_I_222  (.A(\u0/duty_cycle_r[2]_net_1 ), 
        .B(\u0/counter[2]_net_1 ), .Y(\u0/N_17 ));
    AO1C \u0/un1_duty_cycle_r_0_I_172  (.A(\u0/duty_cycle_r[12]_net_1 )
        , .B(\u0/counter[12]_net_1 ), .C(\u0/N_60 ), .Y(\u0/N_66_0 ));
    DFN1C1 \u0/counter[13]  (.D(\u0/counter_5[13]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[13]_net_1 ));
    AND3 \u0/un1_counter_0_I_38  (.A(\u0/DWACT_BL_EQUAL_0_E_9[0] ), .B(
        \u0/DWACT_BL_EQUAL_0_E_9[1] ), .C(\u0/DWACT_BL_EQUAL_0_E_9[2] )
        , .Y(\u0/DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_7[0] ));
    OA1 \u0/un1_counter_0_I_214  (.A(\u0/N_41_0 ), .B(\u0/N_40_1 ), .C(
        \u0/N_39_0 ), .Y(\u0/DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] ));
    OA1A \u0/un1_counter_0_I_213  (.A(\u0/N_36_0 ), .B(\u0/N_38_0 ), 
        .C(\u0/N_37_0 ), .Y(\u0/N_41_0 ));
    DFN1E0C1 \u0/duty_cycle_r[6]  (.D(\data[6] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_299_i ), .Q(\u0/duty_cycle_r[6]_net_1 ));
    OR3 \u2/status_ns_1_iv_0[0]  (.A(\u2/N_73 ), .B(\u2/N_143 ), .C(
        \u2/N_74 ), .Y(\u2/status_ns[0] ));
    OA1A \u0/un1_duty_cycle_r_0_I_230  (.A(\u0/N_20 ), .B(\u0/N_22 ), 
        .C(\u0/N_21 ), .Y(\u0/N_25 ));
    OR2A \u0/un1_duty_cycle_r_0_I_52  (.A(\u0/counter[31]_net_1 ), .B(
        \u0/duty_cycle_r[31]_net_1 ), .Y(\u0/N_135 ));
    XNOR2 \u0/un1_counter_0_I_136  (.A(\u0/counter[16]_net_1 ), .B(
        \u0/clock_divide_r[16]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_6[1] ));
    DFN1E0C1 \u0/duty_cycle_r[27]  (.D(\data[3] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_347_i ), .Q(\u0/duty_cycle_r[27]_net_1 ));
    OR3C \u2/un1_status_6_0_0_a3_0  (.A(\u2/N_140 ), .B(
        \u2/un1_status_6_0_0_a3_0_1_0_net_1 ), .C(\u2/N_42_i_0 ), .Y(
        \u2/N_72 ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_118  (.A(
        \u0/duty_cycle_r[15]_net_1 ), .B(\u0/counter[15]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E[5] ));
    XNOR2 \u0/un1_counter_0_I_3  (.A(\u0/counter[21]_net_1 ), .B(
        \u0/clock_divide_r[21]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_10[2] ));
    AND3 \u0/un8_counter_I_65  (.A(\u0/DWACT_FINC_E[6] ), .B(
        \u0/counter[9]_net_1 ), .C(\u0/counter[10]_net_1 ), .Y(
        \u0/N_116 ));
    AND3 \u0/un8_counter_I_149  (.A(\u0/counter[0]_net_1 ), .B(
        \u0/counter[1]_net_1 ), .C(\u0/counter[2]_net_1 ), .Y(
        \u0/DWACT_FINC_E[34] ));
    AO1C \u0/un1_duty_cycle_r_0_I_91  (.A(\u0/counter[20]_net_1 ), .B(
        \u0/duty_cycle_r[20]_net_1 ), .C(\u0/N_108_0 ), .Y(\u0/N_110 ));
    BUFF \u2/clk1m_inferred_clock_0_0  (.A(\u2/clk1m_net_1 ), .Y(
        \u2/clk1m_0_0 ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_189  (.A(\u0/duty_cycle_r[9]_net_1 )
        , .B(\u0/counter[9]_net_1 ), .Y(\u0/DWACT_BL_EQUAL_0_E[4] ));
    OA1 \u0/un1_counter_0_I_59  (.A(\u0/N_141_1 ), .B(\u0/N_140_0 ), 
        .C(\u0/N_139_0 ), .Y(\u0/DWACT_CMPLE_PO0_DWACT_COMP0_E_2[0] ));
    DFN1E0C1 \u0/clock_divide_r[30]  (.D(\data[6] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_283_i ), .Q(\u0/clock_divide_r[30]_net_1 ));
    DFN1C1 \u2/cou[3]  (.D(\u2/cou_16[3] ), .CLK(\u2/clk1m_0 ), .CLR(
        rst_c), .Q(\u2/cou[3]_net_1 ));
    AND3 \u0/un8_counter_I_216  (.A(\u0/DWACT_FINC_E[24] ), .B(
        \u0/DWACT_FINC_E[23] ), .C(\u0/DWACT_FINC_E[26] ), .Y(\u0/N_9 )
        );
    OA1A \u0/un1_counter_0_I_226  (.A(\u0/counter[3]_net_1 ), .B(
        \u0/clock_divide_r[3]_net_1 ), .C(\u0/N_17_0 ), .Y(\u0/N_21_0 )
        );
    DFN1E0C1 \u0/clock_divide_r[18]  (.D(\data[2] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_267_i ), .Q(\u0/clock_divide_r[18]_net_1 ));
    OR2A \u0/un1_duty_cycle_r_0_I_169  (.A(\u0/counter[14]_net_1 ), .B(
        \u0/duty_cycle_r[14]_net_1 ), .Y(\u0/N_63 ));
    OR2A \u0/un1_counter_0_I_204  (.A(\u0/clock_divide_r[6]_net_1 ), 
        .B(\u0/counter[6]_net_1 ), .Y(\u0/N_32_0 ));
    XA1 \u0/counter_5[1]  (.A(\u0/counter[0]_net_1 ), .B(
        \u0/counter[1]_net_1 ), .C(\u0/I_248 ), .Y(
        \u0/counter_5[1]_net_1 ));
    DFN1C1 \u0/counter[3]  (.D(\u0/counter_5[3]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[3]_net_1 ));
    DFN1C1 \u0/counter[31]  (.D(\u0/counter_5[31]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[31]_net_1 ));
    AND2 \u0/un8_counter_I_101  (.A(\u0/counter[15]_net_1 ), .B(
        \u0/counter[16]_net_1 ), .Y(\u0/DWACT_FINC_E[11] ));
    XA1 \u0/counter_5[12]  (.A(\u0/N_111 ), .B(\u0/counter[12]_net_1 ), 
        .C(\u0/un1_counter_1 ), .Y(\u0/counter_5[12]_net_1 ));
    NOR2A \u2/status_ns_0_0_a3[1]  (.A(\u2/status[0]_net_1 ), .B(
        \u2/status_ns_1_iv_0_o2_0[0]_net_1 ), .Y(\u2/N_88 ));
    AND3 \u0/un8_counter_I_185  (.A(\u0/DWACT_FINC_E[29] ), .B(
        \u0/DWACT_FINC_E[30] ), .C(\u0/DWACT_FINC_E[21] ), .Y(
        \u0/N_31 ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_136  (.A(
        \u0/duty_cycle_r[16]_net_1 ), .B(\u0/counter[16]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_0[1] ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_121  (.A(
        \u0/duty_cycle_r[17]_net_1 ), .B(\u0/counter[17]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E[7] ));
    DFN1C1 \u0/counter[18]  (.D(\u0/counter_5[18]_net_1 ), .CLK(GLA), 
        .CLR(rst_c), .Q(\u0/counter[18]_net_1 ));
    DFN1E0C1 \u0/duty_cycle_r[31]  (.D(\data[7] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_347_i ), .Q(\u0/duty_cycle_r[31]_net_1 ));
    OA1A \u0/un1_duty_cycle_r_0_I_58  (.A(\u0/N_136_0 ), .B(\u0/N_138 )
        , .C(\u0/N_137 ), .Y(\u0/N_141_0 ));
    NOR2A \u0/un1_duty_cycle_r_0_I_149  (.A(\u0/counter[15]_net_1 ), 
        .B(\u0/duty_cycle_r[15]_net_1 ), .Y(\u0/ACT_LT4_E[0] ));
    DFN1E0C1 \u0/clock_divide_r[1]  (.D(\data[1] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_235_i ), .Q(\u0/clock_divide_r[1]_net_1 ));
    XNOR2 \u0/un1_duty_cycle_r_0_I_12  (.A(\u0/duty_cycle_r[30]_net_1 )
        , .B(\u0/counter[30]_net_1 ), .Y(\u0/DWACT_BL_EQUAL_0_E[11] ));
    NOR2A \u2/count_5[0]  (.A(\u2/clk1m6_net_1 ), .B(
        \u2/count[0]_net_1 ), .Y(\u2/count_5[0]_net_1 ));
    OR2A \u0/un1_duty_cycle_r_0_I_56  (.A(\u0/duty_cycle_r[31]_net_1 ), 
        .B(\u0/counter[31]_net_1 ), .Y(\u0/N_139 ));
    AND3 \u0/un1_counter_0_I_139  (.A(\u0/DWACT_BL_EQUAL_0_E_6[0] ), 
        .B(\u0/DWACT_BL_EQUAL_0_E_6[1] ), .C(
        \u0/DWACT_BL_EQUAL_0_E_6[2] ), .Y(
        \u0/DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[0] ));
    AND2 \u0/un8_counter_I_176  (.A(\u0/counter[24]_net_1 ), .B(
        \u0/counter[25]_net_1 ), .Y(\u0/DWACT_FINC_E[20] ));
    XNOR2 \u0/un1_counter_0_I_135  (.A(\u0/counter[15]_net_1 ), .B(
        \u0/clock_divide_r[15]_net_1 ), .Y(
        \u0/DWACT_BL_EQUAL_0_E_6[0] ));
    AND3 \u0/un8_counter_I_223  (.A(\u0/DWACT_FINC_E[24] ), .B(
        \u0/DWACT_FINC_E[23] ), .C(\u0/DWACT_FINC_E[27] ), .Y(
        \u0/N_4_0 ));
    OA1A \u0/un1_duty_cycle_r_0_I_54  (.A(\u0/duty_cycle_r[30]_net_1 ), 
        .B(\u0/counter[30]_net_1 ), .C(\u0/N_133 ), .Y(\u0/N_137 ));
    DFN1E0C1 \u0/duty_cycle_r[12]  (.D(\data[4] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_315_i ), .Q(\u0/duty_cycle_r[12]_net_1 ));
    AND3 \u0/un8_counter_I_195  (.A(\u0/DWACT_FINC_E[29] ), .B(
        \u0/DWACT_FINC_E[30] ), .C(\u0/DWACT_FINC_E[23] ), .Y(
        \u0/N_24 ));
    XA1 \u0/counter_5[22]  (.A(\u0/N_61 ), .B(\u0/counter[22]_net_1 ), 
        .C(\u0/un1_counter_0 ), .Y(\u0/counter_5[22]_net_1 ));
    AND2 \u0/un8_counter_I_125  (.A(\u0/counter[18]_net_1 ), .B(
        \u0/counter[19]_net_1 ), .Y(\u0/DWACT_FINC_E[14] ));
    AND2 \u0/un1_duty_cycle_r_0_I_20  (.A(
        \u0/DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[1] ), .B(
        \u0/DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[0] ), .Y(
        \u0/DWACT_COMP0_E_0[1] ));
    AND3 \u0/un8_counter_I_172  (.A(\u0/DWACT_FINC_E[29] ), .B(
        \u0/DWACT_FINC_E[13] ), .C(\u0/DWACT_FINC_E[19] ), .Y(
        \u0/N_40 ));
    OR2A \u0/un1_duty_cycle_r_0_I_90  (.A(\u0/counter[23]_net_1 ), .B(
        \u0/duty_cycle_r[23]_net_1 ), .Y(\u0/N_109 ));
    NOR2A \u0/un1_counter_0_I_168  (.A(\u0/clock_divide_r[10]_net_1 ), 
        .B(\u0/counter[10]_net_1 ), .Y(\u0/N_62_0 ));
    OR2A \u0/un1_counter_0_I_52  (.A(\u0/clock_divide_r[31]_net_1 ), 
        .B(\u0/counter[31]_net_1 ), .Y(\u0/N_135_0 ));
    OR2A \u0/un1_counter_0_I_222  (.A(\u0/counter[2]_net_1 ), .B(
        \u0/clock_divide_r[2]_net_1 ), .Y(\u0/N_17_0 ));
    NOR2A \u0/un1_counter_0_I_154  (.A(\u0/clock_divide_r[18]_net_1 ), 
        .B(\u0/counter[18]_net_1 ), .Y(\u0/ACT_LT4_E_0[5] ));
    AND3 \u0/un1_duty_cycle_r_0_I_18  (.A(
        \u0/DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_3[0] ), .B(
        \u0/DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[1] ), .C(
        \u0/DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[2] ), .Y(
        \u0/DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[0] ));
    OR2B \u2/un1_status_6_0_0_o2_0  (.A(\addr[1] ), .B(\addr_0[0] ), 
        .Y(un1_status_6_0_0_o2_0));
    NOR2A \u0/un1_counter_0_I_156  (.A(\u0/counter[17]_net_1 ), .B(
        \u0/clock_divide_r[17]_net_1 ), .Y(\u0/ACT_LT4_E_0[7] ));
    IOPAD_IN \CLK48M_pad/U0/U0  (.PAD(CLK48M), .Y(\CLK48M_pad/U0/NET1 )
        );
    DFN1E0C1 \u0/duty_cycle_r[24]  (.D(\data[0] ), .CLK(GLA), .CLR(
        rst_c), .E(\u0/N_347_i ), .Q(\u0/duty_cycle_r[24]_net_1 ));
    DFN1E1C1 \u2/data[0]  (.D(\u2/data_5[0] ), .CLK(\u2/clk1m_net_1 ), 
        .CLR(rst_c), .E(\u2/N_42_i_0 ), .Q(\data[0] ));
    AO1C \u0/un1_duty_cycle_r_0_I_229  (.A(\u0/duty_cycle_r[3]_net_1 ), 
        .B(\u0/counter[3]_net_1 ), .C(\u0/N_19_0 ), .Y(\u0/N_24_0 ));