top_ba.sdf

Core_PWM,verilog语言编写

 (DELAY
  (ABSOLUTE
     (PORT A (8.76:10.62:11.60) (8.15:9.89:10.80))
     (IOPATH A Y (1.94:2.38:2.69) (2.63:3.23:3.65))
     (PORT B (8.95:10.86:11.85) (8.38:10.17:11.10))
     (IOPATH B Y (3.27:4.01:4.53) (3.36:4.13:4.66))
     (PORT C (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH C Y (3.45:4.24:4.79) (3.58:4.40:4.97))
  )
 )
 )
 (CELL
 (CELLTYPE "XNOR2")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_118)
 (DELAY
  (ABSOLUTE
     (PORT A (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH A Y (1.85:3.23:3.65) (2.13:2.70:3.05))
     (PORT B (11.40:13.82:15.09) (10.52:12.75:13.92))
     (IOPATH B Y (3.58:6.20:7.00) (3.25:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "XNOR2")
 (INSTANCE u0\/un1_counter_0_I_3)
 (DELAY
  (ABSOLUTE
     (PORT A (12.15:14.73:16.09) (11.15:13.52:14.76))
     (IOPATH A Y (1.85:3.23:3.65) (2.13:2.70:3.05))
     (PORT B (11.87:14.40:15.72) (10.93:13.26:14.47))
     (IOPATH B Y (3.58:6.20:7.00) (3.25:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE u0\/un8_counter_I_65)
 (DELAY
  (ABSOLUTE
     (PORT A (10.18:12.35:13.48) (9.50:11.52:12.58))
     (IOPATH A Y (2.83:3.47:3.92) (2.50:3.07:3.47))
     (PORT B (16.07:19.49:21.28) (14.93:18.10:19.77))
     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
     (PORT C (4.90:5.94:6.48) (4.59:5.57:6.08))
     (IOPATH C Y (3.58:4.40:4.97) (3.45:4.24:4.79))
  )
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE u0\/un8_counter_I_149)
 (DELAY
  (ABSOLUTE
     (PORT A (2.62:3.18:3.47) (2.42:2.93:3.20))
     (IOPATH A Y (2.83:3.47:3.92) (2.50:3.07:3.47))
     (PORT B (6.32:7.66:8.37) (5.76:6.98:7.62))
     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
     (PORT C (6.28:7.62:8.32) (5.88:7.13:7.78))
     (IOPATH C Y (3.58:4.40:4.97) (3.45:4.24:4.79))
  )
 )
 )
 (CELL
 (CELLTYPE "AO1C")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_91)
 (DELAY
  (ABSOLUTE
     (PORT A (7.98:9.67:10.56) (7.26:8.80:9.61))
     (IOPATH A Y (2.08:2.55:2.88) (1.98:2.44:2.75))
     (PORT B (2.31:2.80:3.06) (2.18:2.64:2.88))
     (IOPATH B Y (2.44:3.00:3.39) (3.21:3.94:4.45))
     (PORT C (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH C Y (3.79:4.66:5.26) (4.13:5.07:5.72))
  )
 )
 )
 (CELL
 (CELLTYPE "BUFF")
 (INSTANCE u2\/clk1m_inferred_clock_0_0)
 (DELAY
  (ABSOLUTE
     (PORT A (5.62:6.81:7.44) (5.38:6.53:7.13))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
  )
 )
 )
 (CELL
 (CELLTYPE "XNOR2")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_189)
 (DELAY
  (ABSOLUTE
     (PORT A (9.15:11.10:12.12) (8.60:10.43:11.38))
     (IOPATH A Y (1.85:3.23:3.65) (2.13:2.70:3.05))
     (PORT B (12.77:15.48:16.91) (11.83:14.34:15.66))
     (IOPATH B Y (3.58:6.20:7.00) (3.25:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "OA1")
 (INSTANCE u0\/un1_counter_0_I_59)
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (5.30:6.51:7.35) (3.94:4.84:5.46))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (4.90:6.03:6.80) (3.27:4.01:4.53))
     (PORT C (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH C Y (2.83:3.47:3.92) (2.62:3.22:3.63))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0C1")
 (INSTANCE u0\/clock_divide_r\[30\])
 (DELAY
  (ABSOLUTE
     (PORT D (8.26:10.01:10.93) (7.71:9.35:10.21))
     (PORT CLK (4.43:5.37:5.86) (4.53:5.49:5.99))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (4.18:5.07:5.53) (4.30:5.22:5.70))
     (IOPATH CLR Q () (2.87:3.53:3.99))
     (PORT E (11.41:13.84:15.11) (10.77:13.06:14.26))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (2.71:3.34:3.76))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
     (SETUP (posedge E) (posedge CLK) (3.28:4.02:4.54))
     (SETUP (negedge E) (posedge CLK) (2.34:2.88:3.25))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE u2\/cou\[3\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.10:2.54:2.77) (2.03:2.46:2.69))
     (PORT CLK (8.21:9.96:10.87) (7.79:9.45:10.32))
     (IOPATH CLK Q (2.84:3.48:3.93) (3.52:4.32:4.88))
     (PORT CLR (4.51:5.46:5.97) (4.61:5.59:6.10))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.84:4.72:5.32))
     (SETUP (negedge D) (posedge CLK) (3.84:4.72:5.32))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (2.80:3.22:3.22))
     (WIDTH (negedge CLK) (3.10:3.56:3.56))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE u0\/un8_counter_I_216)
 (DELAY
  (ABSOLUTE
     (PORT A (8.85:10.73:11.71) (8.28:10.04:10.96))
     (IOPATH A Y (2.63:3.23:3.65) (1.94:2.38:2.69))
     (PORT B (12.28:14.89:16.26) (11.35:13.77:15.03))
     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
     (PORT C (10.06:12.20:13.32) (9.38:11.38:12.43))
     (IOPATH C Y (3.58:4.40:4.97) (3.45:4.24:4.79))
  )
 )
 )
 (CELL
 (CELLTYPE "OA1A")
 (INSTANCE u0\/un1_counter_0_I_226)
 (DELAY
  (ABSOLUTE
     (PORT A (2.32:2.81:3.07) (2.19:2.66:2.90))
     (IOPATH A Y (5.03:6.18:6.97) (3.43:4.21:4.75))
     (PORT B (1.92:2.33:2.54) (1.83:2.23:2.43))
     (IOPATH B Y (4.86:5.97:6.74) (3.51:4.31:4.87))
     (PORT C (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH C Y (2.83:3.47:3.92) (2.62:3.22:3.63))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0C1")
 (INSTANCE u0\/clock_divide_r\[18\])
 (DELAY
  (ABSOLUTE
     (PORT D (10.41:12.62:13.78) (9.88:11.98:13.08))
     (PORT CLK (4.46:5.41:5.91) (4.55:5.52:6.03))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (4.20:5.09:5.56) (4.33:5.25:5.74))
     (IOPATH CLR Q () (2.87:3.53:3.99))
     (PORT E (9.73:11.81:12.89) (8.95:10.85:11.85))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (2.71:3.34:3.76))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
     (SETUP (posedge E) (posedge CLK) (3.28:4.02:4.54))
     (SETUP (negedge E) (posedge CLK) (2.34:2.88:3.25))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2A")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_169)
 (DELAY
  (ABSOLUTE
     (PORT A (5.29:6.41:7.00) (4.87:5.91:6.45))
     (IOPATH A Y (2.51:3.08:3.48) (2.89:3.55:4.01))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (2.77:3.40:3.84) (3.48:4.28:4.83))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2A")
 (INSTANCE u0\/un1_counter_0_I_204)
 (DELAY
  (ABSOLUTE
     (PORT A (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH A Y (2.51:3.08:3.48) (2.89:3.55:4.01))
     (PORT B (3.16:3.83:4.18) (2.91:3.53:3.85))
     (IOPATH B Y (2.77:3.40:3.84) (3.48:4.28:4.83))
  )
 )
 )
 (CELL
 (CELLTYPE "XA1")
 (INSTANCE u0\/counter_5\[1\])
 (DELAY
  (ABSOLUTE
     (PORT A (8.26:10.02:10.94) (7.70:9.34:10.20))
     (IOPATH A Y (1.86:3.19:3.60) (2.13:2.69:3.04))
     (PORT B (7.43:9.01:9.84) (6.89:8.36:9.13))
     (IOPATH B Y (3.45:4.43:5.00) (3.94:6.53:7.37))
     (PORT C (2.47:3.00:3.28) (2.33:2.83:3.09))
     (IOPATH C Y (3.47:4.27:4.82) (3.84:4.72:5.32))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE u0\/counter\[3\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.53:5.50:6.00) (4.61:5.59:6.10))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (4.48:5.44:5.94) (4.55:5.51:6.02))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE u0\/counter\[31\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.59:5.57:6.08) (4.67:5.66:6.18))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (4.53:5.49:5.99) (4.60:5.58:6.09))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "AND2")
 (INSTANCE u0\/un8_counter_I_101)
 (DELAY
  (ABSOLUTE
     (PORT A (7.94:9.63:10.51) (7.41:8.98:9.81))
     (IOPATH A Y (2.63:3.23:3.65) (2.77:3.40:3.84))
     (PORT B (9.91:12.02:13.13) (9.31:11.30:12.33))
     (IOPATH B Y (2.78:3.42:3.86) (3.38:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "XA1")
 (INSTANCE u0\/counter_5\[12\])
 (DELAY
  (ABSOLUTE
     (PORT A (8.25:10.01:10.92) (7.51:9.10:9.94))
     (IOPATH A Y (2.64:3.47:3.92) (2.45:3.44:3.88))
     (PORT B (10.77:13.06:14.26) (10.25:12.43:13.57))
     (IOPATH B Y (3.45:4.43:5.00) (3.94:6.53:7.37))
     (PORT C (4.00:4.85:5.29) (3.66:4.44:4.84))
     (IOPATH C Y (3.47:4.27:4.82) (3.84:4.72:5.32))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE u2\/status_ns_0_0_a3\[1\])
 (DELAY
  (ABSOLUTE
     (PORT A (6.68:8.10:8.85) (6.21:7.54:8.23))
     (IOPATH A Y (2.78:3.42:3.86) (3.38:4.15:4.69))
     (PORT B (2.23:2.70:2.95) (2.09:2.53:2.77))
     (IOPATH B Y (2.63:3.23:3.65) (2.77:3.40:3.84))
  )
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE u0\/un8_counter_I_185)
 (DELAY
  (ABSOLUTE
     (PORT A (15.40:18.68:20.39) (14.66:17.78:19.41))
     (IOPATH A Y (2.83:3.47:3.92) (2.50:3.07:3.47))
     (PORT B (7.10:8.61:9.40) (6.67:8.08:8.83))
     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
     (PORT C (4.25:5.15:5.63) (3.93:4.76:5.20))
     (IOPATH C Y (3.58:4.40:4.97) (3.45:4.24:4.79))
  )
 )
 )
 (CELL
 (CELLTYPE "XNOR2")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_136)
 (DELAY
  (ABSOLUTE
     (PORT A (9.16:11.11:12.13) (8.45:10.25:11.19))
     (IOPATH A Y (1.85:3.23:3.65) (2.13:2.70:3.05))
     (PORT B (10.02:12.15:13.27) (9.33:11.32:12.36))
     (IOPATH B Y (3.58:6.20:7.00) (3.25:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "XNOR2")
 (INSTANCE u0\/un1_duty_cycle_r_0_I_121)
 (DELAY
  (ABSOLUTE
     (PORT A (4.81:5.83:6.37) (4.50:5.46:5.96))
     (IOPATH A Y (1.85:3.23:3.65) (2.13:2.70:3.05))
     (PORT B (12.05:14.62:15.96) (11.23:13.62:14.87))
     (IOPATH B Y (3.58:6.20:7.00) (3.25:4.15:4.69))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE u0\/counter\[18\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.56:5.54:6.04) (4.65:5.64:6.15))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (4.50:5.46:5.96) (4.58:5.55:6.06))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0C1")
 (INSTANCE u0\/duty_cycle_r\[31\])
 (DELAY
  (ABSOLUTE
     (PORT D (11.96:14.50:15.84) (11.25:13.64:14.89))
     (PORT CLK (4.36:5.29:5.78) (4.47:5.43:5.92))