control.tcl

Core_PWM,verilog语言编写

# Created by Libero Project Manager 8.0.1.13
# Tue Sep 25 08:35:28 2007

# (NEW DESIGN)

# create a new design
new_design -name "control" -family "Fusion"
set_device -die "AFS600" -package "256 FBGA"

# set default back-annotation base-name
set_defvar "BA_NAME" "control_ba"

# set working directory
set_defvar "DESDIR" "C:/Actelprj/PWM/designer/impl1"

# set back-annotation output directory
set_defvar "BA_DIR" "C:/Actelprj/PWM/designer/impl1"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VERILOG"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "control.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/control.edn} \
-format "sdc"  {..\..\synthesis\control_sdc.sdc}

# save the design database
save_design {control.adb}

show_device_selection_wizard