pwm_top.pdc

Core_PWM,verilog语言编写

# Actel Physical design constraints file
# Version: 8.0 SP1 8.0.1.13
# Design Name: top 
# Input Netlist Format: edif 
# Family: Fusion , Die: AFS600 , Package: 256 FBGA , Speed grade: -2 
# Date generated: Mon Oct 15 12:31:21 2007 

#
# IO banks setting
#

set_iobank Bank4 -vcci 3.30 -fixed no
set_iobank Bank3 -vcci 3.30 -fixed yes
set_iobank Bank2 -vcci 3.30 -fixed no
set_iobank Bank1 -vcci 3.30 -fixed no
set_iobank Bank0 -vcci 3.30 -fixed no

#
# I/O constraints
#

set_io pwmout -iostd LVTTL -REGISTER Yes -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname D10 -fixed yes
set_io rst -iostd LVTTL -REGISTER No -RES_PULL None -SCHMITT_TRIGGER Off -IN_DELAY Off -pinname K11 -fixed yes
set_io CLK48M -iostd LVTTL -REGISTER No -RES_PULL None -SCHMITT_TRIGGER Off -IN_DELAY Off -pinname J1 -fixed yes