top_sdc.sdc

Core_PWM,verilog语言编写

# Synplicity, Inc. constraint file
# C:\Actelprj\PWM\constraint\top_sdc.sdc
# Written on Tue Sep 25 15:19:07 2007
# by Synplify Pro, Synplify Pro 8.6.2H Scope Editor

#
# Collections
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# Clocks
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# Clock to Clock
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# Inputs/Outputs
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# Registers
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# Multicycle Path
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# False Path
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# Path Delay
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# Attributes
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define_attribute          {rst} syn_noclockbuf {1}

#
# I/O standards
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# Compile Points
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# Other Constraints
#