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Core_PWM,verilog语言编写

    AND2 un8_counter_I_220 (.A(\DWACT_FINC_E[26] ), .B(
        \counter[30]_net_1 ), .Y(\DWACT_FINC_E[27] ));
    AND2 un8_counter_I_176 (.A(\counter[24]_net_1 ), .B(
        \counter[25]_net_1 ), .Y(\DWACT_FINC_E[20] ));
    AO1 un1_counter_0_I_243 (.A(\DWACT_CMPLE_PO2_DWACT_COMP0_E_0[1] ), 
        .B(I_238), .C(\DWACT_CMPLE_PO2_DWACT_COMP0_E[0] ), .Y(I_243));
    AO1 un1_duty_cycle_r_0_I_104 (.A(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_3[1] ), .B(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] ), .C(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[0] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_0[2] ));
    AO1C un1_counter_0_I_95 (.A(\counter[22]_net_1 ), .B(
        \clock_divide_r[22]_net_1 ), .C(N_109_0), .Y(N_114_0));
    AND2 un1_counter_0_I_40 (.A(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[1] ), .B(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_7[0] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_2[1] ));
    DFN1C1 \counter[17]  (.D(\counter_5[17]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[17]_net_1 ));
    OR2A un1_duty_cycle_r_0_I_205 (.A(\duty_cycle_r[7]_net_1 ), .B(
        \counter[7]_net_1 ), .Y(N_33));
    NOR2B \counter_5[3]  (.A(I_13_0), .B(I_248), .Y(
        \counter_5[3]_net_1 ));
    AND3 un8_counter_I_114 (.A(\DWACT_FINC_E[28] ), .B(
        \DWACT_FINC_E[10] ), .C(\DWACT_FINC_E[12] ), .Y(N_81));
    AND3 un8_counter_I_111 (.A(\DWACT_FINC_E[0] ), .B(
        \DWACT_FINC_E[2] ), .C(\DWACT_FINC_E[5] ), .Y(
        \DWACT_FINC_E[28] ));
    NOR2A un1_duty_cycle_r_0_I_155 (.A(\ACT_LT4_E[4] ), .B(
        \ACT_LT4_E[5] ), .Y(\ACT_LT4_E[6] ));
    XNOR2 un1_duty_cycle_r_0_I_136 (.A(\duty_cycle_r[16]_net_1 ), .B(
        \counter[16]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[1] ));
    DFN1C1 \counter[4]  (.D(\counter_5[4]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[4]_net_1 ));
    XNOR2 un1_duty_cycle_r_0_I_11 (.A(\duty_cycle_r[29]_net_1 ), .B(
        \counter[29]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E[10] ));
    NOR2B \counter_5[16]  (.A(I_98), .B(I_248_1), .Y(
        \counter_5[16]_net_1 ));
    AO1C un1_duty_cycle_r_0_I_93 (.A(\duty_cycle_r[21]_net_1 ), .B(
        \counter[21]_net_1 ), .C(N_106), .Y(N_112));
    DFN1C1 \counter[10]  (.D(\counter_5[10]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[10]_net_1 ));
    AND3 un8_counter_I_30 (.A(\DWACT_FINC_E[0] ), .B(\DWACT_FINC_E[1] )
        , .C(\counter[5]_net_1 ), .Y(N_141));
    NOR2B \counter_5[23]  (.A(I_156), .B(I_248_0), .Y(
        \counter_5[23]_net_1 ));
    DFN1E0C1 \duty_cycle_r[27]  (.D(data[3]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[27]_net_1 ));
    XOR2 un8_counter_I_73 (.A(N_111), .B(\counter[12]_net_1 ), .Y(I_73)
        );
    NOR2A un1_duty_cycle_r_0_I_74 (.A(\counter[24]_net_1 ), .B(
        \duty_cycle_r[24]_net_1 ), .Y(\ACT_LT3_E[0] ));
    GND GND_i (.Y(GND));
    DFN1C1 \counter[13]  (.D(\counter_5[13]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[13]_net_1 ));
    AND3 un8_counter_I_223 (.A(\DWACT_FINC_E[24] ), .B(
        \DWACT_FINC_E[23] ), .C(\DWACT_FINC_E[27] ), .Y(N_4_0));
    OR2A un1_counter_0_I_90 (.A(\clock_divide_r[23]_net_1 ), .B(
        \counter[23]_net_1 ), .Y(N_109_0));
    NOR2A un1_counter_0_I_74 (.A(\clock_divide_r[24]_net_1 ), .B(
        \counter[24]_net_1 ), .Y(\ACT_LT3_E_0[0] ));
    AND2A un1_counter_0_I_151 (.A(\clock_divide_r[16]_net_1 ), .B(
        \counter[16]_net_1 ), .Y(\ACT_LT4_E_0[2] ));
    OR2A un1_duty_cycle_r_0_I_150 (.A(\counter[16]_net_1 ), .B(
        \duty_cycle_r[16]_net_1 ), .Y(\ACT_LT4_E[1] ));
    XNOR2 un1_counter_0_I_36 (.A(\counter[30]_net_1 ), .B(
        \clock_divide_r[30]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_7[3] ));
    AO1C un1_counter_0_I_174 (.A(\counter[13]_net_1 ), .B(
        \clock_divide_r[13]_net_1 ), .C(N_63_0), .Y(N_68_0));
    DFN1E0C1 \clock_divide_r[25]  (.D(data[1]), .CLK(GLA), .CLR(rst_c), 
        .E(N_283_i), .Q(\clock_divide_r[25]_net_1 ));
    AND3 un8_counter_I_185 (.A(\DWACT_FINC_E[29] ), .B(
        \DWACT_FINC_E[30] ), .C(\DWACT_FINC_E[21] ), .Y(N_31));
    XNOR2 un1_counter_0_I_66 (.A(\counter[24]_net_1 ), .B(
        \clock_divide_r[24]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_8[0] ));
    OA1A un1_counter_0_I_213 (.A(N_36), .B(I_210), .C(N_37), .Y(I_213));
    AND3 un1_counter_0_I_17 (.A(\DWACT_BL_EQUAL_0_E_0[9] ), .B(
        \DWACT_BL_EQUAL_0_E_0[10] ), .C(\DWACT_BL_EQUAL_0_E_0[11] ), 
        .Y(\DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[3] ));
    OR2A un1_duty_cycle_r_0_I_90 (.A(\counter[23]_net_1 ), .B(
        \duty_cycle_r[23]_net_1 ), .Y(N_109));
    DFN1E0C1 \clock_divide_r[14]  (.D(data[6]), .CLK(GLA), .CLR(rst_c), 
        .E(N_251_i), .Q(\clock_divide_r[14]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_net_1));
    NOR2A un1_counter_0_I_155 (.A(\ACT_LT4_E_0[4] ), .B(
        \ACT_LT4_E_0[5] ), .Y(\ACT_LT4_E_0[6] ));
    DFN1E0C1 \duty_cycle_r[2]  (.D(data[2]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_40_e_net_1), .Q(\duty_cycle_r[2]_net_1 ));
    DFN1C1 \counter[12]  (.D(\counter_5[12]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[12]_net_1 ));
    DFN1E0C1 \clock_divide_r[8]  (.D(data[0]), .CLK(GLA), .CLR(rst_c), 
        .E(N_251_i), .Q(\clock_divide_r[8]_net_1 ));
    DFN1E0C1 \duty_cycle_r[30]  (.D(data[6]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[30]_net_1 ));
    NOR2A un1_duty_cycle_r_0_I_149 (.A(\counter[15]_net_1 ), .B(
        \duty_cycle_r[15]_net_1 ), .Y(\ACT_LT4_E[0] ));
    DFN1C1 \counter[27]  (.D(\counter_5[27]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[27]_net_1 ));
    XNOR2 un1_duty_cycle_r_0_I_3 (.A(\duty_cycle_r[21]_net_1 ), .B(
        \counter[21]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_4[2] ));
    OA1A un1_counter_0_I_96 (.A(N_110_0), .B(N_112_0), .C(N_111_1), .Y(
        N_115_0));
    DFN1E0C1 \duty_cycle_r[28]  (.D(data[4]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[28]_net_1 ));
    NOR2B \counter_5[28]  (.A(I_203), .B(I_248_0), .Y(
        \counter_5[28]_net_1 ));
    OR2A un1_counter_0_I_157 (.A(\counter[18]_net_1 ), .B(
        \clock_divide_r[18]_net_1 ), .Y(\ACT_LT4_E_0[8] ));
    AND2 un1_duty_cycle_r_0_I_40 (.A(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[1] ), .B(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[0] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_0[1] ));
    OR2A un1_counter_0_I_49 (.A(\clock_divide_r[28]_net_1 ), .B(
        \counter[28]_net_1 ), .Y(N_132_0));
    DFN1E0C1 \clock_divide_r[2]  (.D(data[2]), .CLK(GLA), .CLR(rst_c), 
        .E(clock_divide_r_8_e_net_1), .Q(\clock_divide_r[2]_net_1 ));
    XOR2 un8_counter_I_129 (.A(N_71), .B(\counter[20]_net_1 ), .Y(
        I_129));
    DFN1C1 \counter[20]  (.D(\counter_5[20]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[20]_net_1 ));
    OR2A un1_duty_cycle_r_0_I_88 (.A(\duty_cycle_r[21]_net_1 ), .B(
        \counter[21]_net_1 ), .Y(N_107));
    AND3 un1_duty_cycle_r_0_I_16 (.A(\DWACT_BL_EQUAL_0_E_0[6] ), .B(
        \DWACT_BL_EQUAL_0_E_0[7] ), .C(\DWACT_BL_EQUAL_0_E_0[8] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[2] ));
    AOI1A un1_counter_0_I_158 (.A(\ACT_LT4_E_0[7] ), .B(
        \ACT_LT4_E_0[8] ), .C(\ACT_LT4_E_0[5] ), .Y(\ACT_LT4_E_0[10] ));
    OA1 un1_duty_cycle_r_0_I_214 (.A(N_41), .B(N_40_1), .C(N_39_0), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[0] ));
    XNOR2 un1_counter_0_I_116 (.A(\counter[12]_net_1 ), .B(
        \clock_divide_r[12]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_7[2] ));
    AND2 un1_counter_0_I_39 (.A(\DWACT_BL_EQUAL_0_E_5[4] ), .B(
        \DWACT_BL_EQUAL_0_E_7[3] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[1] ));
    AND3 un1_counter_0_I_69 (.A(\DWACT_BL_EQUAL_0_E_8[2] ), .B(
        \DWACT_BL_EQUAL_0_E_8[1] ), .C(\DWACT_BL_EQUAL_0_E_8[0] ), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_4[1] ));
    DFN1C1 \counter[23]  (.D(\counter_5[23]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[23]_net_1 ));
    AND2 un1_duty_cycle_r_0_I_39 (.A(\DWACT_BL_EQUAL_0_E_1[4] ), .B(
        \DWACT_BL_EQUAL_0_E_2[3] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[1] ));
    XNOR2 un1_duty_cycle_r_0_I_192 (.A(\duty_cycle_r[5]_net_1 ), .B(
        \counter[5]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E[0] ));
    AND2 un1_duty_cycle_r_0_I_20 (.A(
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[1] ), .B(
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[0] ), .Y(
        \DWACT_COMP0_E_0[1] ));
    XNOR2 un1_duty_cycle_r_0_I_66 (.A(\duty_cycle_r[24]_net_1 ), .B(
        \counter[24]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_2[0] ));
    OR2A un1_counter_0_I_222 (.A(\counter[2]_net_1 ), .B(
        \clock_divide_r[2]_net_1 ), .Y(N_17_0));
    DFN1E0C1 \duty_cycle_r[11]  (.D(data[3]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_48_e_net_1), .Q(\duty_cycle_r[11]_net_1 ));
    AO1C un1_duty_cycle_r_0_I_57 (.A(\duty_cycle_r[30]_net_1 ), .B(
        \counter[30]_net_1 ), .C(N_135), .Y(N_140));
    AO1C un1_duty_cycle_r_0_I_210 (.A(\duty_cycle_r[7]_net_1 ), .B(
        \counter[7]_net_1 ), .C(N_32), .Y(N_38));
    DFN1C1 \counter[22]  (.D(\counter_5[22]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[22]_net_1 ));
    DFN1C1 \counter[15]  (.D(\counter_5[15]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[15]_net_1 ));
    XOR2 un8_counter_I_115 (.A(N_81), .B(\counter[18]_net_1 ), .Y(
        I_115));
    NOR2B \counter_5[22]  (.A(I_143), .B(I_248_0), .Y(
        \counter_5[22]_net_1 ));
    OR2A un1_duty_cycle_r_0_I_173 (.A(\duty_cycle_r[14]_net_1 ), .B(
        \counter[14]_net_1 ), .Y(N_67));
    OR2A un1_duty_cycle_r_0_I_75 (.A(\counter[25]_net_1 ), .B(
        \duty_cycle_r[25]_net_1 ), .Y(\ACT_LT3_E[1] ));
    AND3 un8_counter_I_34 (.A(\counter[3]_net_1 ), .B(
        \counter[4]_net_1 ), .C(\counter[5]_net_1 ), .Y(
        \DWACT_FINC_E[2] ));
    XNOR2 un1_counter_0_I_189 (.A(\counter[9]_net_1 ), .B(
        \clock_divide_r[9]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_3[4] ));
    DFN1E0C1 \clock_divide_r[20]  (.D(data[4]), .CLK(GLA), .CLR(rst_c), 
        .E(clock_divide_r_24_e_net_1), .Q(\clock_divide_r[20]_net_1 ));
    AO1 un1_counter_0_I_183 (.A(\DWACT_CMPLE_PO0_DWACT_COMP0_E_1[1] ), 
        .B(\DWACT_CMPLE_PO0_DWACT_COMP0_E_1[2] ), .C(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_1[0] ), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[0] ));
    OR2A un1_counter_0_I_167 (.A(\counter[12]_net_1 ), .B(
        \clock_divide_r[12]_net_1 ), .Y(N_61_1));
    VCC VCC_i (.Y(VCC));
    XNOR2 un1_counter_0_I_120 (.A(\counter[16]_net_1 ), .B(
        \clock_divide_r[16]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_1[6] ));
    AO1C un1_duty_cycle_r_0_I_174 (.A(\duty_cycle_r[13]_net_1 ), .B(
        \counter[13]_net_1 ), .C(N_63), .Y(N_68));
    AOI1A un1_duty_cycle_r_0_I_159 (.A(\ACT_LT4_E[3] ), .B(
        \ACT_LT4_E[6] ), .C(\ACT_LT4_E[10] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E[0] ));
    NOR2A un1_counter_0_I_168 (.A(\clock_divide_r[10]_net_1 ), .B(
        \counter[10]_net_1 ), .Y(N_62_0));
    DFN1E0C1 \clock_divide_r[27]  (.D(data[3]), .CLK(GLA), .CLR(rst_c), 
        .E(N_283_i), .Q(\clock_divide_r[27]_net_1 ));
    DFN1C1 \counter[1]  (.D(\counter_5[1]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[1]_net_1 ));
    XOR2 un8_counter_I_9 (.A(N_157), .B(\counter[2]_net_1 ), .Y(I_9));
    XNOR2 un1_counter_0_I_2 (.A(\counter[27]_net_1 ), .B(
        \clock_divide_r[27]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_2[8] ));
    XOR2 un8_counter_I_210 (.A(N_14), .B(\counter[29]_net_1 ), .Y(
        I_210_0));
    XOR2 un8_counter_I_166 (.A(N_45), .B(\counter[24]_net_1 ), .Y(
        I_166));
    OA1 un1_counter_0_I_231 (.A(N_25_0), .B(N_24_1), .C(N_23_0), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[2] ));
    XNOR2 un1_counter_0_I_191 (.A(\counter[8]_net_1 ), .B(
        \clock_divide_r[8]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_4[3] ));
    AO1C un1_counter_0_I_55 (.A(\counter[29]_net_1 ), .B(
        \clock_divide_r[29]_net_1 ), .C(N_132_0), .Y(N_138_0));
    AND3 un1_counter_0_I_139 (.A(\DWACT_BL_EQUAL_0_E_6[0] ), .B(
        \DWACT_BL_EQUAL_0_E_6[1] ), .C(\DWACT_BL_EQUAL_0_E_6[2] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[0] ));
    DFN1E0C1 \duty_cycle_r[7]  (.D(data[7]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_40_e_net_1), .Q(\duty_cycle_r[7]_net_1 ));
    DFN1E0C1 \duty_cycle_r[22]  (.D(data[6]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_56_e_net_1), .Q(\duty_cycle_r[22]_net_1 ));
    AND2 un1_counter_0_I_195 (.A(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_3[1] ), .B(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_4[0] ), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[1] ));
    DFN1E0C1 \clock_divide_r[29]  (.D(data[5]), .CLK(GLA), .CLR(rst_c), 
        .E(N_283_i), .Q(\clock_divide_r[29]_net_1 ));
    XNOR2 un1_duty_cycle_r_0_I_8 (.A(\duty_cycle_r[26]_net_1 ), .B(
        \counter[26]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[7] ));
    AO1C un1_counter_0_I_229 (.A(\counter[3]_net_1 ), .B(
        \clock_divide_r[3]_net_1 ), .C(N_19_1), .Y(N_24_1));
    DFN1C1 \counter[25]  (.D(\counter_5[25]_net_1 ), .CLK(GLA), .CLR(